Patents by Inventor Sriseshan Srikanth
Sriseshan Srikanth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420036Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.Type: ApplicationFiled: August 31, 2023Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
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Publication number: 20230409336Abstract: In accordance with described techniques for VLIW Dynamic Communication, an instruction that causes dynamic communication of data to at least one processing element of a very long instruction word (VLIW) machine is dispatched to a plurality of processing elements of the VLIW machine. A first count of data communications issued by the plurality of processing elements and a second count of data communications served by the plurality of processing elements are maintained. At least one additional instruction is determined for dispatch to the plurality of processing elements of the VLIW machine based on the first count and the second count. For example, an instruction that is independent of the instruction is determined for dispatch while the first count and the second count are unequal, and an instruction that is dependent on the instruction is determined for dispatch based on the first count and the second count being equal.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez, Vedula Venkata Srikant Bharadwaj, John Kalamatianos
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Publication number: 20230315320Abstract: A page swapping memory protection system tracks accesses to physical memory pages, such as in a table with each row storing a physical memory page address and a counter value. This counter value records the number of accesses (e.g., read access or write accesses) to the corresponding physical memory page. In response to one of the counters exceeding a threshold value, the corresponding physical memory page is swapped with another page in physical memory (e.g., a page the table indicates has a smallest number of accesses). According, unreliability in the physical memory introduced due to frequent accesses to a particular physical memory page is mitigated.Type: ApplicationFiled: March 24, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: SeyedMohammad SeyedzadehDelcheh, Sriseshan Srikanth
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Publication number: 20230306256Abstract: Systems, apparatuses, and methods for scattering floating point values to heterogeneous memory devices are disclosed. An inference engine performs floating point calculations during pre-training and during post-training operations. A scatter unit stores the floating point number values in multiple memories with different error correction capabilities. A first portion of each floating point number value is stored in a first memory having a relatively high error correction capability, and a second portion of each floating point number value is stored in a second memory with a relatively low error correction capability. In one scenario, the first portion includes the sign and exponent fields, while the second portion includes the mantissa field. The resiliency of the inference engine to overcome small errors allows for convergence to the final result in spite of any errors in the retrieved second portion.Type: ApplicationFiled: March 25, 2022Publication date: September 28, 2023Inventors: Sriseshan Srikanth, SeyedMohammad SeyedzadehDelcheh
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Patent number: 11756606Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.Type: GrantFiled: December 13, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
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Publication number: 20230186976Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
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Publication number: 20230128916Abstract: A processing system performs error detection at each of a plurality of layers of a neural network, such as a neural network implemented at a computational analog memory. By performing error detection at the layer level, the processing system is able to account for write errors when updating neural network weights, without waiting for backpropagation based on an output of the neural network. The processing system thereby reduces the amount of time needed to train the network, both by reducing the number of training epochs, and by reducing the length of the individual training epochs.Type: ApplicationFiled: October 27, 2021Publication date: April 27, 2023Inventors: Sriseshan Srikanth, SeyedMohammad SeyedzadehDelcheh
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Publication number: 20230102690Abstract: A method includes, in response to receiving a command from a processing device, reading original data from a set of one or more memory devices based on an address range specified in the command, and transmitting a subset of the original data to the processing device, where the subset includes fewer zero values than the original data.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan
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Patent number: 10191689Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.Type: GrantFiled: December 29, 2016Date of Patent: January 29, 2019Assignee: Intel CorporationInventors: Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney
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Patent number: 10176124Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.Type: GrantFiled: April 1, 2017Date of Patent: January 8, 2019Assignee: Intel CorporationInventors: Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney
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Publication number: 20180285286Abstract: A technology is described for determining an idle page close timeout for a row buffer. An example memory controller may comprise a scoreboard buffer and a predictive timeout engine. The scoreboard buffer may be configured to store a number of page hits and a number of page misses for a plurality of candidate timeout values for an idle page close timeout. The predictive timeout engine may be configured to increment the page hits and the page misses in the scoreboard buffer according to estimated page hit results and page miss results for the candidate timeout values, and identify a candidate timeout value from the scoreboard buffer estimated to maximize the number of page hits to the number of page misses.Type: ApplicationFiled: April 1, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney
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Publication number: 20180188994Abstract: Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory, including a row buffer. The memory controller may include circuitry to determine that a page stored in the row buffer has been idle for a time exceeding a predetermined threshold determine whether the page is exempt from idle page closures, and, based on a determination that the page is exempt, refrain from closing the page. Associated methods are also disclosed.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney