Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.

Abstract: A method includes etching a semiconductor substrate to form a semiconductor strip and trenches on opposite sidewalls of the semiconductor strip. A spacer is formed on a sidewall of the semiconductor strip which is used as an etching mask to extend the trenches down into the semiconductor substrate. A dielectric material is filled into the trenches and then planarized to form insulation regions in the trenches. The insulation regions are recessed. After the recessing, top surfaces of the insulation regions are lower than a top surface of the semiconductor strip and a gate structure may be formed thereon.

Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.

Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.

Abstract: A method includes etching a semiconductor substrate to form a semiconductor strip and trenches on opposite sidewalls of the semiconductor strip. A spacer is formed on a sidewall of the semiconductor strip which is used as an etching mask to extend the trenches down into the semiconductor substrate. A dielectric material is filled into the trenches and then planarized to form insulation regions in the trenches. The insulation regions are recessed. After the recessing, top surfaces of the insulation regions are lower than a top surface of the semiconductor strip and a gate structure may be formed thereon.

Abstract: An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope.

Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.

Abstract: An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope.

Abstract: Disclosed is a seasoning method for an etch chamber for improving the passing rate, comprising the steps of: introducing a wafer or plural control wafers into the etch chamber; introducing reacting gases into the etch chamber; applying power to top and bottom electrodes of the etch chamber to plasmarize the reacting gases; and adjusting the gate valve of the etch chamber to 90 to 100% of the fully open position, thereby reducing the amount of by-products and eliminating the factors for reducing the passing rate. The seasoning method of this invention is based on a low pressure, high flow-rate sluicing mechanism, where the atmospheric flow and high vacuuming ability would remove the maximum amount of polymer particles and flaking from the etch chamber.