Patents by Inventor Srithar Ramesh

Srithar Ramesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ADDRESS RANGE BASED IN-BAND MEMORY ERROR-CORRECTING CODE PROTECTION MODULE WITH SYNDROME BUFFER
    Publication number: 20190332469
    Abstract: An in-band error correcting code (ECC) module intercepts input/output (I/O) operations directed to a memory. The in-band ECC module determines whether the I/O is directed to data that needs to be protected against error. In response to determining that the I/O is directed to data that needs to be protected against error, the in-band ECC module directs a memory controller to store or access ECC data corresponding to the data in a first preassigned area of the memory, and to store or access the data in a second preassigned area of the memory.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 31, 2019
    Inventors: Amir A. RADJAI, Nagi ABOULENEIN, Steve L. GEIGER, Satyajit A. JADHAV, Bezan J. KAPADIA, Vivek KOZHIKKOTTU, Rashmi LAKKUR SUBRAMANYAM, Srithar RAMESH, James M. SHEHADI, Jason D. VAN DYKEN
  • Supply noise filter for clock generator
    Patent number: 6714092
    Abstract: A circuit for removing noise from the power supply of a clock generator. Switching regulator noise from the voltage regulator section can affect a clock chip when it is carried through the power plane or ground plane. In order to remove this, a ferrite bead is placed along the voltage supply line. A bulk capacitor with low equivalent series resistance is connected from the output side of the ferrite bead to ground. By properly selecting the size of the bead and capacitor, the noise is reduced. The result is that the clock does not drift so that functional failures are reduced.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: March 30, 2004
    Assignee: Intel Corporation
    Inventor: Srithar Ramesh
  • Method and apparatus for eliminating contention with dual bus masters
    Patent number: 6438686
    Abstract: A method and apparatus for eliminating contention with dual masters. One method disclosed disables a default bus master, and tests for a second bus master. If the second bus master fails to respond, the default bus master is enabled.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: August 20, 2002
    Assignee: Intel Corporation
    Inventors: Gregory M. Daughtry, Hieu T. Tran, Srithar Ramesh, Andrew J. McRonald