Abstract: An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.

Abstract: An integrated circuit memory cell includes a floating gate, a control gate, and a plurality of inter-poly dielectric (IPD) layers. The IPD layers include an IPD1 layer, an IPD2 layer, and an IPD3 layer, with the IPD2 layer interposed between the IPD1 and IPD3 layers. The IPD2 layer, which may be a nitride, does not flank the floating gate. Thus, no section of the floating gate is laterally between two sections of the IPD2 layer. Also, no section of the IPD2 layer of a first memory cell is between the floating gate of the first memory cell and a floating gate of an immediate adjacent memory cell of the same memory cell string. In some cases, an IPD4 layer is provided between the floating gate and the IPD3 layer. The IPD4 layer is relatively much thinner than layers IPD1-3 and may flank the floating gate, as may the IPD3 layer.

Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

Abstract: The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction.

Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

Abstract: The present invention provides hybrid microelectronic memory device, comprising: (a) a substrate having a surface, a first region of first work function adjacent the surface, and a second region of second work function adjacent the surface and adjacent the first region; (b) a film comprising redox-active molecules on the first and second regions; and (c) an electrode connected to the film. The present invention further provides a hybrid microelectronic memory device, comprising: (a) a substrate having surface and a structure or region such as a diode for increasing the retention time of the device formed adjacent the surface; (b) a film comprising redox-active molecules on or associated with the region or structure; and (c) an electrode connected to the redox active molecules opposite the substrate surface. Methods of using such devices are also described.

Abstract: The present invention provides hybrid microelectronic memory device, comprising: (a) a substrate having a surface, a first region of first work function adjacent the surface, and a second region of second work function adjacent the surface and adjacent the first region; (b) a film comprising redox-active molecules on the first and second regions; and (c) an electrode connected to the film. The present invention further provides a hybrid microelectronic memory device, comprising: (a) a substrate having surface and a structure or region such as a diode for increasing the retention time of the device formed adjacent the surface; (b) a film comprising redox-active molecules on or associated with the region or structure; and (c) an electrode connected to the redox active molecules opposite the substrate surface. Methods of using such devices are also described.