Abstract: A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.

Abstract: A security policy associated with a system is evaluated. The system includes a communication bus having a data bus and a plurality of components interconnected via the communication bus. The system also includes a circuit configured to evaluate a security policy associated with the system by reading at least one data bus signal associated with a transaction between at least two of the plurality of components.

Abstract: A crossbar switching fabric comprising a plurality of crossbar input ports and a plurality of crossbar output ports. The traffic from at least one source is directed to more than one of the plurality of crossbar input ports. The traffic from more than one crossbar output port is directed to at least one destination.

Abstract: A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches.

Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Abstract: The time required to estimate the amount of power that will be consumed by a circuit under design is significantly speeded up. Specifically, the steps involved in power estimation (power model evaluation, aggregation) are implemented as power estimation circuitry that is added to the design of the functional circuit during circuit design. The resulting power-model-enhanced circuit is mapped onto a hardware emulation platform, one of whose outputs is a computation of the estimated power computed by the power estimation circuitry during the emulation. As compared to state-of-the-art commercial power estimation tools, speed-ups from around 10-fold to over 500-fold can be realized.

Abstract: A system comprising at least one host processor, at least one security processor and a first memory that is exclusively accessible only by the security processor.

Abstract: An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.

Abstract: Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.

Abstract: A programmable security processor for efficient execution of security protocols, wherein the instruction set of the processor is enhanced to contain at least one instruction that is used to improve the efficiency of a public-key cryptographic algorithm, and at least one instruction that is used to improve the efficiency of a private-key cryptographic algorithm.

Abstract: A crossbar switching fabric comprising a plurality of crossbar input ports and a plurality of crossbar output ports. The traffic from at least one source is directed to more than one of the plurality of crossbar input ports. The traffic from more than one crossbar output port is directed to at least one destination.