Patents by Inventor Srivatsa Kundalgurki
Srivatsa Kundalgurki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7863149Abstract: In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).Type: GrantFiled: September 9, 2005Date of Patent: January 4, 2011Assignee: Qimonda AGInventors: Srivatsa Kundalgurki, Peter Moll, Dirk Manger, Kristin Schupke, Till Schloesser
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Patent number: 7579253Abstract: Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which results in an electrically conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layers, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.Type: GrantFiled: April 9, 2007Date of Patent: August 25, 2009Assignee: Infineon Technologies AGInventor: Srivatsa Kundalgurki
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Patent number: 7319223Abstract: Method and apparatus for characterizing a recess located on a surface of a substrate are provided. One embodiment of the invention provides a method for characterizing a recess located on a surface of a substrate. In a first step, a measurement tip is positioned directly above the recess. Subsequently, an electrically conductive path is provided between the measurement tip and the bottom of the recess by ionizing a medium located in the recess. A voltage is applied between the measurement tip and the substrate to measure a current flowing between the measurement tip and the bottom of the recess. The recess is characterized on the basis of the magnitude of the measured current. Another embodiment of the invention provides an apparatus for performing the method for characterizing a recess.Type: GrantFiled: September 14, 2004Date of Patent: January 15, 2008Assignee: Infineon Technologies AGInventor: Srivatsa Kundalgurki
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Patent number: 7284558Abstract: The present invention relates to the use of a C1 to C5 alcohol during the cleaning step. With the use of said alcohol, the surface tension of the solution is reduced which allows the application of reduced megasonic power with increased cleaning efficiency.Type: GrantFiled: February 15, 2005Date of Patent: October 23, 2007Assignee: Infineon Technologies AGInventor: Srivatsa Kundalgurki
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Patent number: 7259061Abstract: Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate, forming a first electrode including depositing a metal alloy layer having a first surface and an exposed second surface, etching the exposed second surface of the metal alloy layer thereby increasing the surface roughness of the second surface of the metal alloy layer, forming a capacitor dielectric on the first electrode and forming a second electrode on the capacitor dielectric. By providing a metal alloy layer and etching the second surface of the metal alloy layer, an increased capacitance of the integrated capacitor is achieved.Type: GrantFiled: July 15, 2004Date of Patent: August 21, 2007Assignee: Infineon Technologies AGInventor: Srivatsa Kundalgurki
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Publication number: 20070184659Abstract: Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which results in an electrically conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layers, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.Type: ApplicationFiled: April 9, 2007Publication date: August 9, 2007Applicant: INFINEON TECHNOLOGIES AGInventor: Srivatsa Kundalgurki
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Patent number: 7208095Abstract: Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which leads to a electrical conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layer, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.Type: GrantFiled: December 15, 2004Date of Patent: April 24, 2007Assignee: Infineon Technologies AGInventor: Srivatsa Kundalgurki
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Publication number: 20060180172Abstract: The present invention relates to the use of a C1 to C5 alcohol during the cleaning step. With the use of said alcohol, the surface tension of the solution is reduced which allows the application of reduced megasonic power with increased cleaning efficiency.Type: ApplicationFiled: February 15, 2005Publication date: August 17, 2006Inventor: Srivatsa Kundalgurki
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Patent number: 7084029Abstract: To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.Type: GrantFiled: September 24, 2004Date of Patent: August 1, 2006Assignee: Infineon Technologies, AGInventors: Srivatsa Kundalgurki, Dietmar Temmler, Hans-Peter Moll, Joerg Wiedemann
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Publication number: 20060124582Abstract: Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which leads to a electrical conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layer, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.Type: ApplicationFiled: December 15, 2004Publication date: June 15, 2006Inventor: Srivatsa Kundalgurki
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Publication number: 20060079049Abstract: In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).Type: ApplicationFiled: September 9, 2005Publication date: April 13, 2006Inventors: Srivatsa Kundalgurki, Peter Moll, Dirk Manger, Kristin Schupke, Till Schloesser
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Patent number: 7018893Abstract: Bottom electrodes of stacked capacitor cells are formed by lining a patterned hard mask with a conductive layer. The hard mask is formed by a layered stack. Subsequent to the formation of trenches within the hard mask, the top-most masking layer of the layer stack is laterally recessed. The bottom electrode layer is then deposited to line the trenches. Following this, the bottom electrode layer is removed from the top of the hardmask. Subsequently, the hard mask is removed. As a result, released and free-standing elements of the conductive layer are formed as bottom electrodes that include a hydrophobic contact area in the top part of the bottom electrodes.Type: GrantFiled: December 15, 2004Date of Patent: March 28, 2006Assignee: Infineon Technologies, AGInventor: Srivatsa Kundalgurki
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Publication number: 20060054812Abstract: Method and apparatus for characterizing a recess located on a surface of a substrate are provided. One embodiment of the invention provides a method for characterizing a recess located on a surface of a substrate. In a first step, a measurement tip is positioned directly above the recess. Subsequently, an electrically conductive path is provided between the measurement tip and the bottom of the recess by ionizing a medium located in the recess. A voltage is applied between the measurement tip and the substrate to measure a current flowing between the measurement tip and the bottom of the recess. The recess is characterized on the basis of the magnitude of the measured current. Another embodiment of the invention provides an apparatus for performing the method for characterizing a recess.Type: ApplicationFiled: September 14, 2004Publication date: March 16, 2006Inventor: Srivatsa Kundalgurki
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Patent number: 7005385Abstract: The present invention relates to a method for removing a resist selective to a carbon hard mask including providing an etching plasma comprising of at least hydrogen at a predetermined temperature level and a predetermined pressure level in a reaction chamber, and etching the resist selectively to the mask with said plasma for a predetermined period of time.Type: GrantFiled: December 15, 2003Date of Patent: February 28, 2006Assignee: Infineon Technologies AGInventor: Srivatsa Kundalgurki
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Publication number: 20060032516Abstract: A process for removing residue from one or more surfaces of chamber components exposed to the interior of a semiconductor process chamber. A plasma chamber is supplied with a gas mixture including nitrogen (N2) and hydrogen (H2), the nitrogen and hydrogen being included in volume % from 2 to 10 of hydrogen and from 98 to 90 of nitrogen, thereby forming a plasma in the plasma chamber so as to decompose a portion of the nitrogen (N2) and hydrogen (H2) to atomic N and/or H. The interior of the semiconductor process chamber is thus exposed to at least a portion of the atomic N and/or H.Type: ApplicationFiled: July 30, 2004Publication date: February 16, 2006Applicants: Infineon Technologies AG, Novellus Systems, Inc.Inventors: Srivatsa Kundalgurki, Haruhiro Goto, David Chen
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Publication number: 20060014343Abstract: Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate, forming a first electrode including depositing a metal alloy layer having a first surface and an exposed second surface, etching the exposed second surface of the metal alloy layer thereby increasing the surface roughness of the second surface of the metal alloy layer, forming a capacitor dielectric on the first electrode and forming a second electrode on the capacitor dielectric. By providing a metal alloy layer and etching the second surface of the metal alloy layer, an increased capacitance of the integrated capacitor is achieved.Type: ApplicationFiled: July 15, 2004Publication date: January 19, 2006Inventor: Srivatsa Kundalgurki
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Publication number: 20050130421Abstract: The present invention relates to a method for removing a resist selective to a carbon hard mask including providing an etching plasma comprising of at least hydrogen at a predetermined temperature level and a predetermined pressure level in a reaction chamber, and etching the resist selectively to the mask with said plasma for a predetermined period of time.Type: ApplicationFiled: December 15, 2003Publication date: June 16, 2005Applicant: Infineon Technologies AGInventor: Srivatsa Kundalgurki
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Publication number: 20050093049Abstract: To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.Type: ApplicationFiled: September 24, 2004Publication date: May 5, 2005Inventors: Srivatsa Kundalgurki, Dietmar Temmler, Hans-Peter Moll, Joerg Wiedemann