Patents by Inventor Srivatsan Chellappa

Srivatsan Chellappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190155999
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Patent number: 10262119
    Abstract: An authenticating service of a chip having an intrinsic identifier (ID) is provided. The authenticating device includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Patent number: 9780788
    Abstract: Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 3, 2017
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Srivatsan Chellappa, Vinay Vashishtha, Aditya Gujja
  • Patent number: 9734272
    Abstract: This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 15, 2017
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan Wheeler Patterson, Chandarasekaran Ramamurthy, Srivatsan Chellappa
  • Publication number: 20170220784
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Patent number: 9690927
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Publication number: 20170117895
    Abstract: Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 27, 2017
    Applicant: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Srivatsan Chellappa, Vinay Vashishtha, Aditya Gujja
  • Patent number: 9424308
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
  • Patent number: 9396143
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
  • Publication number: 20160171045
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 16, 2016
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
  • Patent number: 9343185
    Abstract: A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Srivatsan Chellappa, Dean L. Lewis
  • Publication number: 20160085702
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
  • Patent number: 9268863
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: February 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
  • Patent number: 9219722
    Abstract: A first copy of an intrinsic ID of a first node may be stored on a second node. The first node may receive a challenge that causes it to generate a second copy of its intrinsic ID. The second copy and a random value may be used as inputs of a function to generate a first code. The first code is transmitted to the second node. The second node decodes the first code using its local copies of the random value and/or the intrinsic ID. The second node checks the decoded information against its local information and authenticates the first node if there is a match.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srivatsan Chellappa, Toshiaki Kirihata, Sami Rosenblatt
  • Publication number: 20150363517
    Abstract: This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 17, 2015
    Applicant: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan Wheeler Patterson, Chandarasekaran Ramamurthy, Srivatsan Chellappa
  • Publication number: 20150347592
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 3, 2015
    Applicant: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
  • Publication number: 20150186639
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 2, 2015
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Publication number: 20150163211
    Abstract: A first copy of an intrinsic ID of a first node may be stored on a second node. The first node may receive a challenge that causes it to generate a second copy of its intrinsic ID. The second copy and a random value may be used as inputs of a function to generate a first code. The first code is transmitted to the second node. The second node decodes the first code using its local copies of the random value and/or the intrinsic ID. The second node checks the decoded information against its local information and authenticates the first node if there is a match.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 11, 2015
    Applicant: International Business Machines Corporation
    Inventors: Srivatsan Chellappa, Toshiaki Kirihata, Sami Rosenblatt
  • Patent number: 9038133
    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Srivatsan Chellappa, Subramanian S. Iyer, Toshiaki Kirihata, Sami Rosenblatt
  • Publication number: 20150089329
    Abstract: A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: John E. Barth, JR., Srivatsan Chellappa, Dean L. Lewis