Abstract: An embodiment of an image processor device includes technology to fetch a feature point data set from outside a local memory, locally store three or more fetched feature point data sets in the local memory, compute orientation information for each fetched feature point data set, compute first descriptor information based on the computed orientation information and a first locally stored feature point data set in parallel with a fetch and local store of a second feature point data set in the local memory, and compute second descriptor information based on the computed orientation information and the second locally stored feature point data set in parallel with the compute of the first descriptor information. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an image processor device includes technology to fetch a feature point data set from outside a local memory, locally store three or more fetched feature point data sets in the local memory, compute orientation information for each fetched feature point data set, compute first descriptor information based on the computed orientation information and a first locally stored feature point data set in parallel with a fetch and local store of a second feature point data set in the local memory, and compute second descriptor information based on the computed orientation information and the second locally stored feature point data set in parallel with the compute of the first descriptor information. Other embodiments are disclosed and claimed.

Abstract: A processor may include a plurality of processing elements and a hardware accelerator for selecting data elements. The hardware accelerator may: access an input data set comprising a set of data elements, each data element having a score value; increment bin counters based on the score values of the set of data elements, each bin counter to count a number of data elements with an associated score value; determine a cumulative sum of count values for a sequence of bin counters, the sequence beginning with a first bin counter of the plurality of bin counters; identify a second bin counter in the sequence of bin counters at which the cumulative sum reaches a selection quantity N; and generate an output data set based on a comparison of the set of data elements to a threshold score associated with the second bin counter.

Abstract: A processor may include a plurality of processing elements and a hardware accelerator for selecting data elements. The hardware accelerator may: access an input data set comprising a set of data elements, each data element having a score value; increment bin counters based on the score values of the set of data elements, each bin counter to count a number of data elements with an associated score value; determine a cumulative sum of count values for a sequence of bin counters, the sequence beginning with a first bin counter of the plurality of bin counters; identify a second bin counter in the sequence of bin counters at which the cumulative sum reaches a selection quantity N; and generate an output data set based on a comparison of the set of data elements to a threshold score associated with the second bin counter.