Patents by Inventor Ssu-Hui Lu

Ssu-Hui Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10969618
    Abstract: An opposite substrate including a substrate, first light-shielding patterns, second light-shielding patterns, a planarization layer and support members is provided. The support members are located in primary support regions and secondary support regions of the opposite substrate. The first light-shielding patterns respectively extend along a first direction, and a material of the first light-shielding patterns includes an organic material. The second light-shielding patterns respectively extend along a second direction, and a material of the second light-shielding patterns includes metal. The first light-shielding patterns and the second light-shielding patterns are respectively located at opposite sides of the planarization layer. Alternatively, the first light-shielding patterns and the second light-shielding patterns are located at the same side of the planarization layer, and the planarization layer has openings respectively overlapped with the support members located in the secondary support regions.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 6, 2021
    Assignee: Au Optronics Corporation
    Inventors: Ssu-Hui Lu, Jia-Hong Ye, Kuo-Yu Huang
  • Patent number: 10969636
    Abstract: An active device substrate includes a substrate, first to third scan lines, a first data line, a second data line, a first active device, and a first pixel electrode. The first scan line, the second scan line, and the third scan line are extending along a first direction. The first data line and the second data line are extending along a second direction. The first active device includes a first gate, a second gate, a first semiconductor pattern layer, a first source, and a first drain. The first gate is electrically connected to the first scan line. The second gate is electrically connected to the second scan line. The first scan line and the second scan line transmit different driving signals. The first source is electrically connected to the first data line. The first pixel electrode is electrically connected to the first drain of the first active device.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 6, 2021
    Assignee: Au Optronics Corporation
    Inventors: Ssu-Hui Lu, Wei-Hung Kuo
  • Publication number: 20200371390
    Abstract: An active device substrate includes a substrate, first to third scan lines, a first data line, a second data line, a first active device, and a first pixel electrode. The first scan line, the second scan line, and the third scan line are extending along a first direction. The first data line and the second data line are extending along a second direction. The first active device includes a first gate, a second gate, a first semiconductor pattern layer, a first source, and a first drain. The first gate is electrically connected to the first scan line. The second gate is electrically connected to the second scan line. The first scan line and the second scan line transmit different driving signals. The first source is electrically connected to the first data line. The first pixel electrode is electrically connected to the first drain of the first active device.
    Type: Application
    Filed: September 11, 2019
    Publication date: November 26, 2020
    Applicant: Au Optronics Corporation
    Inventors: Ssu-Hui Lu, Wei-Hung Kuo
  • Patent number: 10332918
    Abstract: A pixel structure including a first pixel unit, a second pixel unit, a first insulating layer, and a common electrode is provided. The first and second pixel units are disposed on a substrate, and includes a first drain and a first pixel electrode, and a second drain and a second pixel electrode, respectively. The first insulating layer covers the first and second drains. The first and second pixel electrodes are disposed on the first insulating layer, and the first insulating layer has first and second contact holes uncovering the first and second drains, respectively. The common electrode is disposed on the first insulating layer, and is electrically insulated from the first and second pixel electrodes, and has a common opening. When projected onto the substrate, the first and second contact holes are disposed within a region of the common opening.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 25, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Ssu-Hui Lu, Chih-Chung Su, Ming-Hsien Lee
  • Publication number: 20170263653
    Abstract: A pixel structure including a first pixel unit, a second pixel unit, a first insulating layer, and a common electrode is provided. The first and second pixel units are disposed on a substrate, and includes a first drain and a first pixel electrode, and a second drain and a second pixel electrode, respectively. The first insulating layer covers the first and second drains. The first and second pixel electrodes are disposed on the first insulating layer, and the first insulating layer has first and second contact holes uncovering the first and second drains, respectively. The common electrode is disposed on the first insulating layer, and is electrically insulated from the first and second pixel electrodes, and has a common opening. When projected onto the substrate, the first and second contact holes are disposed within a region of the common opening.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 14, 2017
    Inventors: Ssu-Hui LU, Chih-Chung SU, Ming-Hsien LEE
  • Publication number: 20160299381
    Abstract: A liquid crystal display panel includes a first substrate, a second substrate, at least one liquid crystal layer, a first pixel array and a second pixel array. The liquid crystal layer is interposed between the first substrate and the second substrate. The first pixel array is disposed in a first display region of the first substrate, where the first pixel array includes a plurality of first transmissive sub-pixels arranged in columns and rows and disposed adjacent to each other. The second pixel array is disposed in a second display region of the first substrate, and the second pixel array includes a plurality of reflective sub-pixels arranged in columns and rows.
    Type: Application
    Filed: October 12, 2015
    Publication date: October 13, 2016
    Inventors: Ssu-Hui Lu, Ming-Hsien Lee
  • Patent number: 9252167
    Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has a transistor region and a transparent region adjacent to each other. The gate electrode is disposed on the transistor region. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region has a second thickness less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are electrically connected to the channel layer. The pixel electrode is disposed on the dielectric layer which is disposed on the transparent region. The pixel electrode is electrically connected to the drain electrode.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: February 2, 2016
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Jia-Hong Ye, Ssu-Hui Lu, Wu-Hsiung Lin, Chao-Chien Chiu, Ming-Hsien Lee, Chia-Tien Peng, Wei-Ming Huang
  • Patent number: 9224868
    Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.
    Type: Grant
    Filed: February 15, 2015
    Date of Patent: December 29, 2015
    Assignee: AU Optronics Corp.
    Inventors: Ssu-Hui Lu, Ming-Hsien Lee
  • Publication number: 20150162453
    Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.
    Type: Application
    Filed: February 15, 2015
    Publication date: June 11, 2015
    Inventors: Ssu-Hui Lu, Ming-Hsien Lee
  • Patent number: 8999775
    Abstract: A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 7, 2015
    Assignee: AU Optronics Corp.
    Inventors: Ssu-Hui Lu, Ming-Hsien Lee
  • Publication number: 20150028336
    Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has a transistor region and a transparent region adjacent to each other. The gate electrode is disposed on the transistor region. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region has a second thickness less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are electrically connected to the channel layer. The pixel electrode is disposed on the dielectric layer which is disposed on the transparent region. The pixel electrode is electrically connected to the drain electrode.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 29, 2015
    Inventors: Jia-Hong YE, Ssu-Hui LU, Wu-Hsiung LIN, Chao-Chien CHIU, Ming-Hsien LEE, Chia-Tien PENG, Wei-Ming HUANG
  • Patent number: 8865532
    Abstract: A method for manufacturing an active device array substrate includes providing a flexible substrate having a transistor region and a transparent region; forming a gate electrode on the transistor region; sequentially forming a dielectric layer and a semiconductor layer to cover the gate electrode and the flexible substrate; removing a part of the semiconductor layer to form a channel layer above the gate electrode and removing a thickness of the dielectric layer disposed on the transparent region, such that a portion of the dielectric layer on the gate electrode has a first thickness, and another portion of the dielectric layer on the transparent region has a second thickness less than the first thickness; respectively forming a source electrode and a drain electrode on opposite sides of the channel layer; and forming a pixel electrode electrically connected to the drain electrode.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: October 21, 2014
    Assignee: AU Optronics Corporation
    Inventors: Jia-Hong Ye, Ssu-Hui Lu, Wu-Hsiung Lin, Chao-Chien Chiu, Ming-Hsien Lee, Chia-Tien Peng, Wei-Ming Huang
  • Publication number: 20140284606
    Abstract: A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.
    Type: Application
    Filed: May 29, 2013
    Publication date: September 25, 2014
    Inventors: Ssu-Hui Lu, Ming-Hsien Lee
  • Publication number: 20140084291
    Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has at least one transistor region and at least one transparent region adjacent to each other. The gate electrode is disposed on the transistor region of the flexible substrate. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region of the flexible substrate has a second thickness. The second thickness is less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are disposed on opposite sides of the channel layer and are electrically connected to the channel layer.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Applicant: AU Optronics Corporation
    Inventors: Jia-Hong YE, Ssu-Hui Lu, Wu-Hsiung Lin, Chao-Chien Chiu, Ming-Hsien Lee, Chia-Tien Peng, Wei-Ming Huang