Patents by Inventor Ssu-I Fu

Ssu-I Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607882
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10566285
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: February 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10546922
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq, Tsung-Mu Yang
  • Patent number: 10541304
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 10529825
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10529856
    Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: January 7, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Man-Ling Lu, Yu-Hsiang Hung, Chung-Fu Chang, Yen-Liang Wu, Wen-Jiun Shen, Chia-Jong Liu, Ssu-I Fu, Yi-Wei Chen
  • Publication number: 20190362981
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Publication number: 20190296124
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.
    Type: Application
    Filed: April 11, 2018
    Publication date: September 26, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10418251
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Patent number: 10395991
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190221469
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10347526
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate structure, and a conductive element. The gate structure is on the substrate. The gate structure includes a gate electrode and a cap layer on the gate electrode. The conductive element is adjoined with an outer surface of the gate structure. The conductive element includes a lower conductive portion and an upper conductive portion electrically connected on the lower conductive portion and adjoined with the cap layer. The lower conductive portion and the upper conductive portion have an interface therebetween. The interface is below an upper surface of the cap layer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20190206672
    Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.
    Type: Application
    Filed: February 11, 2019
    Publication date: July 4, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Publication number: 20190172752
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10256146
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: April 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chao-Hung Lin, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 10249488
    Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10141432
    Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20180331223
    Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 15, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Man-Ling Lu, Yu-Hsiang Hung, Chung-Fu Chang, Yen-Liang Wu, Wen-Jiun Shen, Chia-Jong Liu, Ssu-I Fu, Yi-Wei Chen
  • Patent number: 10103175
    Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20180269288
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq