Abstract: A system and method for optimizing a design layout by identifying features for abutment where shapes of the features that trigger the abutment are overlapping or within a predefined proximity of each other. The abutment process is implemented for features that have overlapping pins or that will have overlapping pins when abutted. Connectivity of abutted features is analyzed for the overlapped pins; pins of one of the abutted features are swapped so that at least one overlapping set of horizontal pins is connected to a same net; and a pin of the abutted features can be shortened as necessary to prevent short-circuit between pins connected to different nets. The overlapping pins are then merged. Pins can be shortened by cutting the pin or by adjusting pin style or pin size.

Abstract: A computer-implemented method to perform context-sensitive incremental design rule checking (DRC) for an integrated circuit (IC). An incremental DRC engine checks design rule violations between a set of environment shapes and a set of active shapes. If no design rule violations are found, the set of active shapes will be added into the set of environment shapes. Furthermore, the incremental DRC engine can be embedded into placement tools, routing tools, or interactive layout editing tools to check design rule violations and help generate DRC error free layouts.