Abstract: The present invention relates to an ultra-low power (ULP) MOS diode. The diode has a first and a second terminal. It comprises an n-MOS transistor having a channel, a first N+ doped diffusion region at one extremity of the channel and a second N+ diffusion region at the other extremity of the channel, and a p-MOS transistor having a channel and a first P+ doped diffusion region at one extremity of the channel and a second P+ diffusion region at the other extremity of the channel. The first N+ diffusion region of the n-MOS transistor is coupled to the first P+ diffusion region of the p-MOS transistor, the gate of the n-MOS transistor is coupled to the second P+ diffusion region of the p-MOS transistor, and the gate of the p-MOS transistor is coupled to the second N+ diffusion region of the n-MOS transistor.

Abstract: Ultra-low power basic blocks and their uses The present invention relates to ultra-low power (ULP) electronic circuits which do not dissipate more than 10 &mgr;W, preferably not more than 1 &mgr;W. An ultra-low power device comprising a series connection of an n-MOS transistor and a p-MOS transistor each having a source and a drain, whereby the source of the n-MOS transistor is coupled with the source of the p-MOS transistor is provided. Both transistors are such that the absolute values of their threshold voltages are different, and that the absolute value of the relative difference of both threshold voltages is between 0.9 and 1.3 Volts. Each of the transistors in the ultra-low power device having at least one gate, these gates may be coupled together to form a common gate. Different applications of these basic blocks are given, such as ULP reference voltage, a ULP level shifter, a ULP voltage multiplier, a ULP OTA. Also a new diode is described.