Patents by Inventor Stéphane Colomines

Stéphane Colomines has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8912857
    Abstract: A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hugues Beaulaton, Thierry Cassagnes, Stéphane Colomines, Didier Salle
  • Patent number: 8654006
    Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christophe Landez, Hugues Beaulaton, Thierry Cassagnes, Stephane Colomines, Robert G. Gach, Akbar Ghazinour, Hao Li, Gilles Montoriol, Didier Salle, Pierre Savary
  • Publication number: 20130187719
    Abstract: A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
    Type: Application
    Filed: April 18, 2008
    Publication date: July 25, 2013
    Applicant: Freescale Semiconductor, Inc
    Inventors: Hugues Beaulaton, Thierry Cassagnes, Stéphane Colomines, Didier Salle
  • Publication number: 20110285575
    Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
    Type: Application
    Filed: February 13, 2009
    Publication date: November 24, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Christophe Landez, Hugues Beaulaton, Thierry Cassagnes, Stephane Colomines, Robert G. Gach, Akbar Ghazinour, Hao Li, Gilles Montoriol, Didier Salle, Pierre Savary
  • Patent number: 7880516
    Abstract: A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: February 1, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hugues Beaulaton, Stephane Colomines, Philippe Gorisse
  • Publication number: 20080265958
    Abstract: A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 30, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Hugues Beaulaton, Stephane Colomines, Philippe Gorisse