Patents by Inventor Stéphane Denorme
Stéphane Denorme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11621051Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.Type: GrantFiled: January 12, 2022Date of Patent: April 4, 2023Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (ROUSSET) SASInventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
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Patent number: 11355503Abstract: A device includes at least three memory cells. For each cell, there is a first doped semiconductor area and a switch coupling the cell to the first area. First doped semiconductor zones connect the first areas together. A memory can include a number of the devices. For example, the cells can be arranged in a matrix, each device defining a row of the matrix.Type: GrantFiled: December 10, 2019Date of Patent: June 7, 2022Assignee: STMICROELECTRONICS SAInventors: Stephane Denorme, Philippe Candelier
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Publication number: 20220139491Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.Type: ApplicationFiled: January 12, 2022Publication date: May 5, 2022Inventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
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Patent number: 11250930Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.Type: GrantFiled: December 10, 2019Date of Patent: February 15, 2022Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (ROUSSET) SASInventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
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Patent number: 11164647Abstract: A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.Type: GrantFiled: December 13, 2019Date of Patent: November 2, 2021Assignee: STMICROELECTRONICS SAInventors: Stephane Denorme, Philippe Candelier
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Publication number: 20200203356Abstract: A device includes at least three memory cells. For each cell, there is a first doped semiconductor area and a switch coupling the cell to the first area. First doped semiconductor zones connect the first areas together. A memory can include a number of the devices. For example, the cells can be arranged in a matrix, each device defining a row of the matrix.Type: ApplicationFiled: December 10, 2019Publication date: June 25, 2020Inventors: Stephane Denorme, Philippe Candelier
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Publication number: 20200202972Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.Type: ApplicationFiled: December 10, 2019Publication date: June 25, 2020Inventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
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Publication number: 20200202966Abstract: A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.Type: ApplicationFiled: December 13, 2019Publication date: June 25, 2020Inventors: Stephane Denorme, Philippe Candelier
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Patent number: 9881928Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.Type: GrantFiled: January 24, 2017Date of Patent: January 30, 2018Assignee: STMICROELECTRONICS SAInventors: Stéphane Denorme, Philippe Candelier
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Publication number: 20170301681Abstract: A configurable read only memory (ROM) including a number of memory cells. The memory cells include first-type memory cells that are electrically-programmable antifuses and second-type memory cells that are antifuses programmed by masking.Type: ApplicationFiled: December 13, 2016Publication date: October 19, 2017Applicant: STMicroelectronics SAInventors: Stephane Denorme, Philippe Candelier
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Publication number: 20170133390Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Inventors: Stéphane Denorme, Philippe Candelier
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Patent number: 9589968Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.Type: GrantFiled: November 25, 2015Date of Patent: March 7, 2017Assignee: STMicroelectronics SAInventors: Stéphane Denorme, Philippe Candelier
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Publication number: 20160343720Abstract: An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.Type: ApplicationFiled: November 25, 2015Publication date: November 24, 2016Inventors: Stéphane Denorme, Philippe Candelier
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Publication number: 20160307640Abstract: A memory cell of the one-time-programmable type is programmed by application of a programming voltage having a value sufficient to obtain a breakdown of a dielectric of a capacitor within the cell. A programming circuit generates the programming voltage as a variable voltage that varies as a function of a temperature (T) of the cell. In particular, the programming voltage varies based on a variation law decreasing as a function of the temperature.Type: ApplicationFiled: December 2, 2015Publication date: October 20, 2016Applicant: STMicroelectronics SAInventors: Philippe Candelier, Antoine Benoist, Stephane Denorme, Joel Damiens
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Patent number: 9275891Abstract: A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer.Type: GrantFiled: May 29, 2013Date of Patent: March 1, 2016Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics (Crolles 2) SASInventors: Claire Fenouillet-Beranger, Stéphane Denorme
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Patent number: 8936993Abstract: A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released.Type: GrantFiled: December 22, 2010Date of Patent: January 20, 2015Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SASInventors: Claire Fenouillet-Béranger, Stéphane Denorme, Philippe Coronel
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Patent number: 8877600Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.Type: GrantFiled: December 12, 2013Date of Patent: November 4, 2014Assignees: STMicroelectronics, Inc., STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Claire Fenouillet-Beranger, Stephane Denorme, Nicolas Loubet, Qing Liu, Emmanuel Richard, Pierre Perreau
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Publication number: 20140170834Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics, Inc., STMicroelectronics S.A.Inventors: Claire Fenouillet-Beranger, Stephane Denorme, Nicolas Loubet, Qing Liu, Emmanuel Richard, Pierre Perreau
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Patent number: 8674443Abstract: A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.Type: GrantFiled: June 20, 2011Date of Patent: March 18, 2014Assignees: Commissariat à l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SASInventors: Philippe Coronel, Claire Fenouillet-Beranger, Stephane Denorme, Olivier Thomas
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Publication number: 20130323903Abstract: A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer.Type: ApplicationFiled: May 29, 2013Publication date: December 5, 2013Inventors: Claire Fenouillet-Beranger, Stéphane Denorme