Abstract: In a general aspect, a method for sharing a memory between two functional entities can include assigning, to the first functional entity, a first data transformation function and a first inverse transformation function, and assigning, to the second functional entity a second data transformation function and a second inverse transformation function. The second inverse data transformation function can be incompatible with the first data transformation function and the first inverse data transformation function can be incompatible with the second data transformation function.

Abstract: In a general aspect, a method for sharing a memory between two functional entities can include assigning, to the first functional entity, a first data transformation function and a first inverse transformation function, and assigning, to the second functional entity a second data transformation function and a second inverse transformation function. The second inverse data transformation function can be incompatible with the first data transformation function and the first inverse data transformation function can be incompatible with the second data transformation function.

Abstract: A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object.

Abstract: A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected area to access data in the protected area while preventing instructions fetched from outside the protected area from accessing data in the protected area.

Abstract: A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices.

Abstract: A method including monitoring whether an externally originating signal reaches a predetermined threshold value in a host, producing an output value based on the monitoring, and identifying a power environment for the host based on the output value is described. Also described is a method for determining the power environment of a host. Systems and hosts for implementing the methods are also described.

Abstract: A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected area to access data in the protected area while preventing instructions fetched from outside the protected area from accessing data in the protected area.

Abstract: A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected area to access data in the protected area while preventing instructions fetched from outside the protected area from accessing data in the protected area.

Abstract: A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices.

Abstract: A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object.

Abstract: A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected area to access data in the protected area while preventing instructions fetched from outside the protected area from accessing data in the protected area.

Abstract: A method including monitoring whether an externally originating signal reaches a predetermined threshold value in a host, producing an output value based on the monitoring, and identifying a power environment for the host based on the output value is described. Also described is a method for determining the power environment of a host. Systems and hosts for implementing the methods are also described.