Abstract: A method and apparatus is disclosed for manipulating vectored data. The method includes shifting bits of packed data comprising M N-bit elements using a bit-level shift step followed by a byte-level shift step. A mask is generated and applied to the intermediate shifted result to produce the final result. A method is disclosed for conditionally transferring data from one general purpose register to another based on data in yet a third general purpose register.

Abstract: A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit.

Abstract: A carry look-ahead digital adder that adds a first operand A of n bits and a second operand B of n bits, with n=2m, including: a first block calculating couples of signals Pq and Gq from the bits of rank q, Aq and Bq, of the first and second operand, with Pq=Aq+Bq and Gq=Aq•Bq; and a second block formed of a regular array of elementary cells of identical functions arranged in n rows and m columns, and elementary cells having two couples of inputs {E1, E2} and {E3, E4} and one couple of outputs {O1,O2}, providing O1=E1•E3 and O2=E2•E4+E3; the elementary cells being interconnected to optimize the propagation speed of the internal signals along a tree-like path.

Abstract: The present invention relates to a digital comparator including a first block receiving on first inputs the bits of a first operand A of n bits and on second inputs the logic complements of the bits of a second operand B of n bits, generating a propagation signal p n = π i = 1 n ⁢ P i ⁢   ⁢ where ⁢   ⁢ P i = A i + B _ i , and a generation signal g