Abstract: A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal are provided by the present invention. In accordance with the invention, the timing loop parameters are first set to an initial set of parameter values. A current frequency error between the data signal and the receiver's clock is calculated. The approximate average value of the frequency error is then determined. After a predetermined amount of time, the absolute value of the difference between the average frequency error and the current frequency error is examined. If the absolute value of the difference is less than a specified threshold, the timing loop parameters are reset to a second set of parameter values contained in a memory. The timing loop parameters are then reset to a third set of parameter values after a second interval of time.

Abstract: A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal are provided by the present invention. In accordance with the invention, the timing loop parameters are first set to an initial set of parameter values. A current frequency error between the data signal and the receiver's clock is calculated. The approximate average value of the frequency error is then determined. After a predetermined amount of time, the absolute value of the difference between the average frequency error and the current frequency error is examined. If the absolute value of the difference is less than a specified threshold, the timing loop parameters are reset to a second set of parameter values contained in a memory. The timing loop parameters are then reset to a third set of parameter values after a second interval of time.

Abstract: A D4 channel bank data bus monitoring scheme automatically determines if a channel unit connector slot is occupied, without having to gain physical access to the interior of the channel bank cabinet and inspect the channel bank's backplane slot positions. To this end, for a respective channel unit connector slot the channel bank's transmit data bus, which is initially pulled high via a pull-up resistor, is monitored for an all `1`s state. If the data on the bus is not all `1`s, then it is inferred that a channel unit is installed. If an all `1`s state is not detected, then, during the next time slot for that channel unit, the bus is decoupled from the pull-up resistor and coupled instead to a `soft` pull-down resistor. If the data on the bus is now all `0`s, it is inferred that the previously read all `1`s condition was due to the fact that no channel unit is installed, and the channel unit connector slot is declared as empty.