Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.

Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.

Abstract: A system and method are provided that maintains a high pH at the wafer surface through the entire polish process and then lowers the pH only when necessary in a controlled fashion after CMP and during the post-polish clean. A fluid having a high pH chemistry and, optionally, surfactants is used instead of deionized water to keep the wafer and polisher components wet and to clean the slurry residue from the polishing pad.

Abstract: A system and method are provided that maintains a high pH at the wafer surface through the entire polish process and then lowers the pH only when necessary in a controlled fashion after CMP and during the post-polish clean. A fluid having a high pH chemistry and, optionally, surfactants is used instead of deionized water to keep the wafer and polisher components wet and to clean the slurry residue from the polishing pad.

Abstract: A system and method are provided that maintains a high pH at the wafer surface through the entire polish process and then lowers the pH only when necessary in a controlled fashion after CMP and during the post-polish clean. A fluid having a high pH chemistry and, optionally, surfactants is used instead of deionized water to keep the wafer and polisher components wet and to clean the slurry residue from the polishing pad.

Abstract: A system and method are provided that maintains a high pH at the wafer surface through the entire polish process and then lowers the pH only when necessary in a controlled fashion after CMP and during the post-polish clean. A fluid having a high pH chemistry and, optionally, surfactants is used instead of deionized water to keep the wafer and polisher components wet and to clean the slurry residue from the polishing pad.

Abstract: An integrated circuit structure includes a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

Abstract: An integrated circuit structure including a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

Abstract: Method and apparatus for detecting the presence of selected types of defects, such as chemical stains from a liquid photoresist material or a liquid dielectric material, on a non-visible chosen surface of a semiconductor water that has undergone at least one processing step. In one embodiment, a support substrate for, the wafer is provided that has a highly reflecting surface adjacent to the chosen surface. The reflecting surface and the chosen surface are moved apart, and the chosen surface is illuminated with light to form an optical image of the chosen surface. The optical image of the chosen surface is reflected in the reflecting surface, and the reflected optical image is examined for the presence of selected types of defects. In another embodiment, a portion of this reflecting surface is initially contiguous to the chosen surface.

Abstract: An improved method for forming vias in an anti-fuse semiconductor device through an oxide layer to an underlying metallic layer. A wet etch is performed on the oxide layer at selected regions where vias are to be formed. The wet etch is controlled such that a first recessed area is formed in the oxide layer at the selected regions. The first recessed area formed by the wet etch extends only partially through the oxide layer towards the underlying metallic layer. Additionally, the first recessed area is formed having a smoothly shaped contour. Next, a dry etch is performed on the oxide layer at the selected regions where the vias are to be formed. The dry etch is performed within the first recessed area. The second recessed area has a smaller cross sectional area than the first recessed area such that the second recessed area is peripherally bordered by the first recessed area.

Abstract: A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.

Abstract: After a metal deposition is patterned using a plasma etch, the metal pattern is sprayed with steam and water. During the spraying the wafer is rotated to ensure proper distribution and removal of the spray. The spray removes chlorine residue from the etch that might otherwise corrode the metal pattern. After the spray, the spin rate is increased to dry the wafer. The net result is a faster and more effective method for chlorine removal from a plasma-etched metal pattern.

Abstract: A metal oxide coating is applied between the conductive base and the magnesium oxide dielectric of the input and/or erase electrode(s) in a plasma display device to prevent break-down of the dielectric.

Abstract: A method for suppressing the objectionable visual flash associated with replacing patterns in a "plasma-charge-transfer" shift mechanism type AC plasma shift display panel. During the erase mode, the load mode, or both, the phase voltage repetition rate is reduced until the time average luminous flux is substantially below the level of human perception in a room ambient light background. Upon entry into the hold mode, the phase voltage repetition rate reverts to a high frequency. The rapid rate generates patterns in the display panel which have a time average luminous flux adequate for viewing in the ambient light background. The visual flash is thereby suppressed without degrading the normal display characteristics of the panel.

Abstract: The display panel includes a gas-filled envelope made up of a base plate and a face plate hermetically sealed together. A cell sheet is disposed between the base plate and face plate, an array of cathode strips is disposed between the base plate and cell sheet, and an array of anodes is disposed between the face plate and cell sheet, with the anodes being disposed at an angle to the cathodes so that each crossing of an anode and cathode and the volume of gas between them define a display cell. The cell sheet includes slots which define rows of separate operating areas on each cathode. In addition, each cathode strip defines a column of operating cathode areas. The panel carries a mercury capsule, whether in the tubulation or in a convenient portion of the cell sheet, and the cell sheet is provided with channels or slots, in communication with the mercury capsule, to facilitate the dispersion of mercury throughout the panel.