Abstract: A node in a packet network such as an ATM network receives a plurality of traffic classes and outputs them to an output link. The invention relates to a technique of scheduling the traffic classes in a time linked fashion at the node based on the bandwidth allocated to each traffic class. Traffic scheduling based strictly on priority may not satisfy delay and loss guarantees of traffic classes when there are many classes with many different priority levels. The rate based scheduling in a time-linked fashion solves these problems by limiting the bandwidth to which each class is accessible. According to one embodiment, the invention uses timeslot values and a linked list of the traffic classes.

Abstract: Systems and methods consistent with the invention write and read data cells to and from a bank of cell buffer memories. The system includes a plurality of memory units for storing data cells. An address memory outputs a memory address and a memory selecting unit selects one of the plurality of memory units based on the outputted memory address. The system then performs a read or write operation at the outputted memory address of the selected memory unit. The system may write data cells to one memory unit while at the same time reading data cells from one of the other memory units.

Abstract: Methods, systems, and networks for tracking multicast cell copies in a switch. The switch includes a plurality of output ports each having an associated output port register, and a port memory controller for receiving a bit map on the enqueue of a cell into the switch. The bit map includes a bit for each output port register. The port memory controller writes to each output port register the bit from the bit map for that port register. The value of a bit in an output port register indicates whether a copy of the enqueued cell is to be transmitted from the output port associated with that output port register.

Abstract: In a multicast cell counting methodology, the use of banked memories for enqueuing and dequeuing a multicast cell count value spreads the memory accesses over multiple memories, yielding a reduction in the number of per memory accesses per cell cycle. A cell count value, representing the number of cell copies to be multicast, is written to a first memory on a cell enqueue, and retrieved from the first memory after a first cell dequeue. The cell count value is decremented to reflect the first cell dequeue, and transferred to a second memory.

Abstract: Techniques of service-rate controls in ATM switches are described, and apparatus for their implementation are devised. The techniques fall in two categories: frequency domain controls, and time-domain controls. The regulators control the service rate on a per-class basis or on a per-connection basis. Some class regulators operate at very high speeds of the order of several gigabits per second and cover a medium number of classes, 32 for example. Other regulators operate at high speeds of the order of several-hundred megabits per second, and cover a very large number of classes, e.g., 10000. A compound regulator which combines both types of regulators is also described. The compound regulators extend the range of controllable classes considerably, covering some 200,000 classes. The main advantages of the regulators of the invention are simplicity, robustness, and high performance.

Abstract: Techniques of service-rate controls in ATM switches are described, and apparatus for their implementation are devised. The techniques fall in two categories: frequency domain controls, and time-domain controls. The regulators control the service rate on a per-class basis or on a per-connection basis. Some class regulators operate at very high speeds of the order of several gigabits per second and cover a medium number of classes, 32 for example. Other regulators operate at high speeds of the order of several-hundred megabits per second, and cover a very large number of classes, e.g., 10000. A compound regulator which combines both types of regulators is also described. The compound regulators extend the range of controllable classes considerably, covering some 200,000 classes. The main advantages of the regulators of the invention are simplicity, robustness, and high performance.

Abstract: A method for scheduling low delay-jitter cell transmissions for multiple streams of Asynchronous Transfer Mode (ATM) traffic from a node is disclosed. Cells belonging to multiple streams of virtual circuits (VCs) and virtual paths (VPs) are stored in the node's memory. A link controller scans a time-space map to determine when a given stream will be sampled and its cells transmitted from the memory out over a link. The time-space map is comprised of time-slots whose spatial positions within the map correspond to times at which cells can be transmitted. A scattering technique, based on reverse-binary or other mapping schemes, ensures that each given stream occupies time-slots that are well-spaced within the time-space map. This ensures that cells belonging to a given stream are transmitted at well-spaced intervals of time.

Abstract: A multi-stage ATM switch has a plurality of inlet stage fabrics, core stage fabrics and outlet stage fabrics. ATM cells routed by the switch have destination fields including (i) an identification of the outlet stage fabric and (ii) an identification of the outlet port. Cells incoming to a given inlet stage fabric are queued up in queues representing each of the outlet stage fabrics. A queue having at least the number of cells as there are core stage fabrics (or one having a lesser number of cells where cells have been waiting longer than an a pre-defined time) is identified and, in a time slot, cells are transmitted from the front of the identified queue, in parallel, one to each of the core stage fabrics (with blank make-up cells being sent, as necessary, where the identified queue had less cells than there are core stage fabrics).