Abstract: A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors.

Abstract: A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth.

Abstract: A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors.

Abstract: A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth.

Abstract: A phase locked loop arrangement (1) beamforming comprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump current source (41, 42) with an adjustment input (?adj) connected to the loop filter (51, 52) to inject an adjustable charge pump current into the loop filter. A constant current source (71, 72) is configured to inject a first predetermined charge current into the loop filter (51, 52). The adjustable charge pump arrangements (31, 32) are connected to the respective phase comparators (21, 22) to provide a voltage control signal (vctrl) to an oscillator (61, 62) of the respective phase adjustable phase locked loop (11, 12) in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (fosc1, fosc2) based on an adjustment signal applied to the adjustment input (?adj).

Abstract: An integrated circuit is disclosed. The integrated circuit includes a set of transceivers comprising a plurality of transceivers, all configured to transmit in the same transmit frequency band and receive in the same receive frequency band. Furthermore, the integrated circuit has a set of frequency synthesizers including a separate frequency synthesizer associated with each transceiver in the set of transceivers, wherein each frequency synthesizer in the set is configured to generate a local-oscillator (LO) signal to its associated transceiver. Moreover, the integrated circuit includes a control circuit configured to control the set of frequency synthesizers such that nearest neighbors in the set of frequency synthesizers generate LO signals at different frequencies (f1, f2, f3, f4).

Abstract: A fractional-N frequency synthesizer circuit is disclosed. It comprises a frequency divider circuit configured to receive a first oscillation signal having a first frequency, to receive a control word indicating a divisor, and to frequency divide the first oscillation signal with the divisor to generate a second oscillation signal having a second frequency, lower than the first frequency. It also comprises a modulator circuit configured to generate a sequence of control words to the frequency divider circuit. The modulator circuit comprises a set of memory elements configured to store an internal state of the modulator circuit in response to a first control signal and to restore the internal state of the modulator circuit in response to a second control signal, thereby enabling a time shift of the sequence of control words. A communication circuit, a communication apparatus, and a method are also disclosed.

Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

Abstract: A fractional-N frequency synthesizer circuit (20, 20a-c) is disclosed. It comprises a frequency divider circuit (70) configured to receive a first oscillation signal having a first frequency, to receive a control word indicating a divisor, and to frequency divide the first oscillation signal with the divisor to generate a second oscillation signal having a second frequency, lower than the first frequency. It also comprises a modulator circuit (80) configured to generate a sequence of control words to the frequency divider circuit. The modulator circuit (80) comprises a set of memory elements (M, M1-MN), configured to store an internal state of the modulator circuit (80) in response to a first control signal and to restore the internal state of the modulator circuit (80) in response to a second control signal, thereby enabling a time shift of the sequence of control words. A communication circuit, a communication apparatus, and a method are also disclosed.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a set of transceivers comprising a plurality of transceivers, all configured to transmit in the same transmit frequency band and receive in the same receive frequency band. Furthermore, the integrated circuit has a set of frequency synthesizers including a separate frequency synthesizer associated with each transceiver in the set of transceivers, wherein each frequency synthesizer in the set is configured to generate a local-oscillator (LO) signal to its associated transceiver. Moreover, the integrated circuit includes a control circuit configured to control the set of frequency synthesizers such that nearest neighbors in the set of frequency synthesizers generate LO signals at different frequencies (f1, f2, f3, f4).

Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

Abstract: A circuit for calibration measurements comprises a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when voltage across the capacitor reaches the voltage across the resistor; and a controller having a clock signal input and connected to the output of the comparator circuit.

Abstract: Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

Abstract: A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.

Abstract: Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

Abstract: An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided.

Abstract: A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed.

Abstract: A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed.

Abstract: A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.

Abstract: The programmable frequency control system presented herein provides frequency programmability and phase noise reduction for signals generated by a plurality of frequency programmable phase-locked loops (PLLs). In general, a modulated data stream input to each of the plurality of PLLs controls the frequency of the signal output by the PLLs. The solution presented herein reduces the phase noise by introducing a time shift to the modulated data stream applied to at least some of the PLLs so that at least some of the PLLs receive time-shifted versions of the modulated data stream relative to other PLLs. In so doing, the solution presented herein decorrelates the quantization noise generated by the plurality of frequency programmable PLLs.