Patents by Inventor Stalinselvaraj Jeyasingh

Stalinselvaraj Jeyasingh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7177967
    Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Stalinselvaraj Jeyasingh, Andrew V. Anderson, Steven M. Bennett, Erik Cota-Robles, Alain Kagi, Gilbert Neiger, Richard Uhlig
  • Patent number: 7127548
    Abstract: In one embodiment, a command pertaining to one or more portions of a register is received from guest software. Further, a determination is made as to whether the guest software has access to all of the requested portions of the register based on indicators within a mask field that correspond to the requested portions of the register. If the guest software has access to all of the requested portions of the register, the command received from the guest software is executed on the requested portions of the register.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Steve Bennett, Andrew V. Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Michael A. Kozuch
  • Patent number: 7124327
    Abstract: In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more filtering criterion. If the determination is positive, control remains with the guest software and is not transferred to the virtual machine monitor (VMM).
    Type: Grant
    Filed: June 29, 2002
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Steve Bennett, Andrew V. Anderson, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Xiang Zou, Michael A. Kozuch
  • Patent number: 7073042
    Abstract: In one embodiment, when it is determined that a modification of content of an active address translation data structure is required, an entry in the active address translation data structure is modified to conform to a corresponding entry in a guest address translation data structure. During the modification, a bit field including one or more access control indicators in the entry of the active address translation data structure is not overwritten with corresponding data from the guest address translation data structure.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Richard Uhlig, Gilbert Neiger, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Steven M Bennett
  • Publication number: 20060130060
    Abstract: In some embodiments, the invention involves a system to deprivilege components of a virtual machine monitor and enable deprivileged service virtual machines (SVMs) to handle selected trapped events. An embodiment of the invention is a hybrid VMM operating on a platform with hardware virtualization support. The hybrid VMM utilizes features from both hypervisor-based and host-based VMM architectures. In at least one embodiment, the functionality of a traditional VMM is partitioned into a small platform-dependent part called a micro-hypervisor (MH) and one or more platform-independent parts called service virtual machines (SVMs). The micro-hypervisor operates at a higher virtual machine (VM) privilege level than any SVM, while the SVM and other VMs may still have access to any instruction set architecture (ISA) privilege level. Other embodiments are described and claimed.
    Type: Application
    Filed: December 10, 2004
    Publication date: June 15, 2006
    Inventors: Andrew Anderson, Steven Bennett, Erik Cota-Robles, Alain Kagi, Gilbert Neiger, Rajesh Madukkarumukumana, Sebastian Schoenberg, Richard Uhlig, Michael Rothman, Vincent Zimmer, Stalinselvaraj Jeyasingh
  • Patent number: 7035963
    Abstract: In one embodiment, a method for resolving address space conflicts includes detecting that a guest operating system attempts to access a region occupied by a first portion of a virtual machine monitor and relocating the first portion of the virtual machine monitor within the first address space to allow the guest operating system to access the region previously occupied by the first portion of the virtual machine monitor.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Publication number: 20060036791
    Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.
    Type: Application
    Filed: October 13, 2005
    Publication date: February 16, 2006
    Inventors: Stalinselvaraj Jeyasingh, Andrew Anderson, Steven Bennett, Erik Cota-Robles, Alain Kagi, Gilbert Neiger, Richard Uhlig
  • Patent number: 6996748
    Abstract: In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more fault filtering criteria. If the determination is positive, the guest software is permitted to disregard the fault.
    Type: Grant
    Filed: June 29, 2002
    Date of Patent: February 7, 2006
    Assignee: Intel Corporation
    Inventors: Richard Uhlig, Andrew V. Anderson, Steve Bennett, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger
  • Publication number: 20060010440
    Abstract: In one embodiment, the present invention includes a method of transitioning control to guest software in a virtual machine from a virtual machine monitor, receiving control following a transition from the virtual machine to the virtual machine monitor upon an event, and determining whether to modify a state of the guest code, a state of the virtual machine monitor or a state of controls. If such a determination is made, the state may be modified and control is transitioned back to the guest software.
    Type: Application
    Filed: July 7, 2004
    Publication date: January 12, 2006
    Inventors: Andrew Anderson, Steven Bennett, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alani Kagi, Michael Goldsmith, Sebastian Schoenberg, Richard Uhlig
  • Publication number: 20060005084
    Abstract: In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Gilbert Neiger, Andrew Anderson, Steven Bennett, Jason Brandt, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Sanjoy Mondal, Rajesh Parthasarathy, Dion Rodgers, Lawrence Smith, Richard Uhlig
  • Publication number: 20050240819
    Abstract: In one embodiment, a method includes receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a single-stepping indicator is set to a single stepping value, and transitioning control to the VM. Further, if an execution of a first instruction in the VM completes successfully, control is transitioned to the VMM following the successful completion of the execution of the first instruction.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 27, 2005
    Inventors: Steven Bennett, Andrew Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Sanjoy Mondal, Jason Brandt
  • Publication number: 20050240700
    Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) upon receiving a request from a virtual machine monitor (VMM), determining that the request to transition control is associated with a request to be informed of an open event window, performing an event window check to determine whether an even window of the VM is open, and transitioning control to the VMM if the event window check indicates that the event window of the VM is open.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 27, 2005
    Inventors: Steven Bennett, Andrew Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig
  • Publication number: 20050240751
    Abstract: In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content of the active translation data structure to conform to the content of the guest translations data structure. The content of the active translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).
    Type: Application
    Filed: February 28, 2005
    Publication date: October 27, 2005
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Patent number: 6907600
    Abstract: In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content of the active translation data structure to conform to the content of the guest translations data structure. The content of the active translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 14, 2005
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Publication number: 20050080965
    Abstract: In one embodiment, a method includes recognizing an interrupt pending during an operation of guest software, determining that the interrupt is to cause a transition of control to a virtual machine monitor (VMM), determining whether the interrupt is to be acknowledged prior to the transition of control to the VMM, and if the interrupt is to be acknowledged, acknowledging the interrupt and transitioning control to the VMM.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 14, 2005
    Inventors: Steven Bennett, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Gilbert Neiger, Richard Uhlig
  • Publication number: 20050080934
    Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 14, 2005
    Inventors: Erik Cota-Robles, Andy Glew, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Gilbert Neiger, Richard Uhlig
  • Publication number: 20050080970
    Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 14, 2005
    Inventors: Stalinselvaraj Jeyasingh, Andrew Anderson, Steven Bennett, Erik Cota-Robles, Alain Kagi, Gilbert Neiger, Richard Uhlig
  • Publication number: 20050080937
    Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 14, 2005
    Inventors: Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Gilbert Neiger, Richard Uhlig
  • Publication number: 20050071840
    Abstract: In one embodiment, a method for handling privileged events in a virtual machine environment includes detecting an occurrence of a privileged event, determining which one of multiple virtual machine monitors (VMMs) is to handle the privileged event, and transitioning control to this VMM.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 31, 2005
    Inventors: Gilbert Neiger, Steven Bennett, Alain Kagi, Stalinselvaraj Jeyasingh, Andrew Anderson, Richard Uhlig, Erik Cota-Robles, Scott Rodgers, Lawrence Smith
  • Publication number: 20050060702
    Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 17, 2005
    Inventors: Steven Bennett, Andrew Anderson, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Xiang Zou, Lawrence Smith, Scott Rodgers