Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

Abstract: Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

Abstract: In a self-aligned contact (SAC) process, a sacrificial etch stop layer is embedded over source/drain regions, i.e., directly over an interlayer dielectric (IDL) disposed over source/drain regions to enable polishing of a nitride capping layer with respect to the interlayer dielectric. The sacrificial etch stop layer may comprise cobalt metal, and is adapted to be removed and replaced with additional ILD material after controlled polishing of the nitride capping layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor gate structures with gate height scaling and methods of manufacture. The method includes: forming at least one dummy gate structure with hardmask material; forming a plurality of materials over source and drain regions on sides of the at least one dummy gate structure; removing upper materials of the hardmask material such that a first material of the hardmask material remains on the dummy gate structure and in combination with a blocking material of the plurality of materials maintains a uniform gate height; forming a replacement gate structure by removing remaining material of the dummy gate structure to form a trench and depositing replacement gate material in the trench; and forming contacts to the source and drain regions.

Abstract: Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.

Abstract: Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.

Abstract: A process for forming a conductive structure includes the formation of a self-aligned, inlaid conductive cap over a cobalt-based contact. The inlaid conductive cap is formed using a damascene process by depositing a conductive layer comprising tungsten or copper over a recessed cobalt-based contact, followed by a CMP step to remove excess portions of the conductive layer. The conductive cap can cooperate with a liner/barrier layer to form an effective barrier to cobalt migration and oxidation.

Abstract: One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.

Abstract: Disclosed are approaches for determining a processing endpoint using individually measured target spectra. More specifically, one approach includes: measuring a white light (WL) target spectra of a semiconductor device on an individual wafer prior to formation of a polishing/planarization material; inputting the WL target spectra to a WL endpoint algorithm of the semiconductor device following formation of the polishing/planarization material; and determining, using the WL endpoint algorithm, the processing endpoint of the polishing/planarization material of the semiconductor device. In another approach, the endpoint measurement process comprises receiving spectra reflected from the semiconductor device during polishing, and comparing the spectra to the WL target spectra, which is previously stored within a storage device. As such, WL target spectra are measured “as is” (e.g., without simplifications, generalizations, assumptions, etc.

Abstract: A method and apparatus for local polishing and deposition control in a process cell is generally provided. In one embodiment, an apparatus for electrochemically processing a substrate is provided that selectively polishes discrete conductive portions of a substrate by controlling an electrical bias profile across a processing area, thereby controlling processing rates between two or more conductive portions of the substrate.

Abstract: A method and apparatus for local polishing and deposition control in a process cell is generally provided. In one embodiment, an apparatus for electrochemically processing a substrate is provided that selectively polishes discrete conductive portions of a substrate by controlling an electrical bias profile across a processing area, thereby controlling processing rates between two or more conductive portions of the substrate.

Abstract: Systems and methods for electrochemically processing a substrate. A contact element defines a substrate contact surface positionable in contact a substrate during processing. In one embodiment, the contact element comprises a wire element. In another embodiment the contact element is a rotating member. In one embodiment, the contact element comprises a noble metal.

Abstract: Systems and methods for electrochemically processing. In one embodiment, a plurality of grooves are formed in a polishing surface of a polishing pad. The grooves are adapted to facilitate the flow of polishing fluid over the polishing pad. Conductive layers are respectively formed in the grooves, wherein the conductive layers are in electrical communication with each other.

Abstract: Techniques for providing exchange market platform for possessing timeshare properties are described herein. In one embodiment, a fair market price (FMP) is determined for possessing a timeshare property for a predetermined period of time in view of supply and demand of a plurality of timeshare properties having similar characteristics available for the predetermined period of time. The FMP is determined independent of buyers and sellers of the plurality of timeshare properties. In response to an offer from a buyer, a trade transaction is executed at FMP if the FMP is more than or equal to the minimum acceptance price (MAP) of a seller currently owning a right of possessing the timeshare property. Other methods and apparatuses are also described.

Abstract: Electrolyte compositions and methods for planarizing a surface of a substrate using the electrolyte compositions are provided. In one aspect, an electrolyte composition includes one or more chelating agents, one or more corrosion inhibitors, and one or more pH adjusting agents. In another aspect, an electrolyte composition includes one or more chelating agents, two or more corrosion inhibitors, and one or more pH adjusting agents. In another aspect, an electrolyte composition includes one or more chelating agents, one or more corrosion inhibitors, one or more pH adjusting agents, and one or more electrically resistive additives.

Abstract: Embodiments of a polishing article for processing a substrate are provided. In one embodiment, a polishing article for processing a substrate comprises a fabric layer having a conductive layer disposed thereover. The conductive layer has an exposed surface adapted to polish a substrate. The fabric layer may be woven or non-woven. The conductive layer may be comprised of a soft material and, in one embodiment, the exposed surface may be planar.

Abstract: Compositions and methods for removal of barrier layer materials by a chemical mechanical polishing technique are provided. In one aspect, the invention provides a composition adapted for removing a barrier layer material in a chemical mechanical polishing technique including at least one reducing agent selected from the group of bicarboxylic acids, tricarboxylic acids, and combinations thereof, at least one reducing agent selected from the group of glucose, hydroxylamine, and combinations thereof, and deionized water, wherein the composition has a pH of about 7 or less. The composition may be used in a method for removing the barrier layer material including applying the composition to a polishing pad and polishing the substrate in the presence of the composition to remove the barrier layer.