Abstract: Methods and systems related to parallel computing using heterogeneous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network to facilitate the execution of the complex computation by the heterogeneous set of computational nodes and in response to the execution of the instructions.

Abstract: Methods and systems related to parallel computing using heterogenous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogenous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network, to facilitate the execution of the complex computation by the heterogenous set of computational nodes, and in response to the execution of the instructions.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes a memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Abstract: In an electronic device including a processor interface and a processor interconnected to the processor interface by a bus, activity on the bus is monitored and in response to inactivity, the processor interface is placed in a lower power consumption mode. While in the lower power consumption mode, processor requests to the processor interface are inhibited.

Abstract: In an electronic device including a processor interface and a processor interconnected to the processor interface by a bus, activity on the bus is monitored and in response to inactivity, the processor interface is placed in a lower power consumption mode. While in the lower power consumption mode, processor requests to the processor interface are inhibited.

Abstract: A method and apparatus for data bus inversion provides for a data bus having a data bus size value, wherein the data bus size value represents the number of bits transferred across the bus in a single transmission, for receiving a new data value having a plurality of new data bits. The method and apparatus further provide for determining the change bit value by comparing the different new data bits with a plurality of current transmission data bits from a current data value. Furthermore, when the change bit value is equal to one-half the data bus size value, the method and apparatus provides for adjusting at least the plurality of new data bits and/or a data bus inversion bit, based on the determination to assert the plurality of new data bits and the data bus inversion bit closer to a bus idle value.