Abstract: An image processor comprises image processing circuitry implementing a plurality of processing layers including a preprocessing layer for received image data and one or more higher processing layers coupled to the preprocessing layer. The image processor further comprises a multi-channel interface including at least first and second image data channels arranged in parallel with one another between the preprocessing layer and a given higher processing layer. The first image data channel is configured to carry partial depth information derived from the received image data to the given higher processing layer, and the second image data channel is configured to carry complete preprocessed frames of the received image data from the preprocessing layer to the given higher processing layer. By way of example only, in a given embodiment the partial depth information comprises depth information determined to have at least a specified level of reliability.

Abstract: A method and system is provided for automatically recognizing geometric points of features in a target design for OPC mask quality calculation. For each feature in the target design, x, y points comprising the feature are traversed and each neighboring pair of points is connected to define respective segments, wherein a set of contiguous segments form a step if the x values of the segments/points all increase or decrease and the same is true for the y values. Physical characteristics of the segments of the respective features are determined by comparing lengths of the segments to one another and to threshold values. Locations of quality measuring points are then determined along particular ones of the segments based on the physical characteristics.

Abstract: A method and system for improving aerial image simulation speeds. The method includes receiving a mask; generating a matrix of node values based on the mask, wherein each node value corresponds to a node of a plurality of nodes in a lattice; performing a one-dimensional (1-D) approximation of a plurality of first approximation values at corresponding first approximation points between pairs of nodes of the plurality of nodes; performing a two-dimensional (2-D) approximation of second approximation values at corresponding second approximation points between pairs of first approximation points, wherein Chebyshev polynomials are used to approximate the first approximation values and the second approximation values. According to the method and system disclosed herein, approximating values using Chebyshev polynomials results in high-resolution aerial images that are generated at faster speeds.

Abstract: The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ideal edge position to obtain the best decision for OPC.

Abstract: The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target layer and the OPC mask layer as either repeating or non-repeating, and for each repeating cell, recognizing geometric points in the target layer to determine quality measuring groups. The method also includes simulating the OPC mask layer based on the quality measuring groups, measuring edge placement errors (EPEs) based on at least one of the geometric points, and providing an EPE layer representing EPEs greater than an EPE threshold.

Abstract: A method and system is provided for performing edge correction on a mask design. Aspects of the invention include initially fragmenting boundaries of the mask design for optical proximity correction, whereby edge segments of the boundaries are moved by a distance value; interpreting the moved edge segments by defining a new endpoint for respective pairs of neighboring edge segments that meet at an angle, the endpoint being a location of where lines on which the edge segments lie intersect, wherein the new endpoint is used to create a smoothed feature, resulting in a smoothed OPC mask; calculating distances between all pairs of comparable edge segments of the smoothed OPC mask; comparing the distances to a design rule limit; for each edge segment having a distance that exceeds the design rule limit, decreasing the segment's distance value; and optimizing the mask design by repeating the above steps until no distance violations are found.

Abstract: The present invention is directed to a method and apparatus for making mask edge corrections using a gradient method for high density chip designs. The present invention uses a newly defined cost function.

Abstract: A method of measuring the quality of a simulated aerial image includes receiving as input a mask pattern for a chip design, simulating an aerial image of the mask pattern, calculating an error area representative of a deviation between an ideal boundary of the chip design and a boundary of the simulated aerial image, calculating maximum and average end-of-line deviations between the ideal boundary of the chip design and the boundary of the simulated aerial image, and displaying a worst quality area in the simulated aerial image as a function of the error area and the maximum and average end-of-line deviations for visual inspection.

Abstract: The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ideal edge position to obtain the best decision for OPC.

Abstract: Local images of photolithographic masks are assigned to classes based on similarity of functions of circuits formed by the images, so that all of the images of a class can be corrected by correcting one of the members. Boundaries of photolithographic masks are corrected for diffusion of light by moving regions based on process light intensity and proximity of close connections. Boundaries are also corrected for shifting of photoactive material in photoresists by calculating the amount of shift based on light intensities at pattern points.

Abstract: A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes exploding calls on an element list to generate an expanded element list, defining a local cover area for each call on the expanded element list, classifying congruent local cover areas into corresponding groups, and performing an OPC procedure for one local cover area in each group By defining the local cover area for each call and grouping congruent local cover areas, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local cover areas. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.

Abstract: The present invention is directed to an optical proximity correction driven hierarchy. A method for constructing a hierarchy of optically independent structures for use in optical proximity correction of a circuit may include receiving an integrated circuit design, the design including geometric circuit elements for providing circuit functions of an integrated circuit. At least a portion of the integrated circuit design is exploded and geometric circuit elements of the exploded integrated circuit design are gathered into optically independent classes. A search is then performed for congruency for each optically independent class.

Abstract: A method of finding an optically periodic structure in a cell layer of an integrated circuit design includes receiving as input a physical representation of a cell layer of an integrated circuit design, finding reference coordinates of a selected portion of the cell layer from the physical representation of a cell layer, selecting an initial element located nearest to the reference coordinates, and constructing a base structure that includes the initial element and a minimum number of elements in the physical representation of the cell layer wherein the base structure may be replicated at an X-offset and a Y-offset to fill the entire selected portion so that for each element in each replica of the base structure there is an identical element at identical coordinates in the physical representation of the cell layer.

Abstract: A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes exploding calls on an element list to generate an expanded element list, defining a local cover area for each call on the expanded element list, classifying congruent local cover areas into corresponding groups, and performing an OPC procedure for one local cover area in each group.

Abstract: A method of finding an optically periodic structure in a cell layer of an integrated circuit design includes receiving as input a physical representation of a cell layer of an integrated circuit design, finding reference coordinates of a selected portion of the cell layer from the physical representation of a cell layer, selecting an initial element located nearest to the reference coordinates, and constructing a base structure that includes the initial element and a minimum number of elements in the physical representation of the cell layer wherein the base structure may be replicated at an X-offset and a Y-offset to fill the entire selected portion so that for each element in each replica of the base structure there is an identical element at identical coordinates in the physical representation of the cell layer.

Abstract: A method of measuring the quality of a simulated aerial image includes receiving as input a mask pattern for a chip design, simulating an aerial image of the mask pattern, calculating an error area representative of a deviation between an ideal boundary of the chip design and a boundary of the simulated aerial image, calculating maximum and average end-of-line deviations between the ideal boundary of the chip design and the boundary of the simulated aerial image, and displaying a worst quality area in the simulated aerial image as a function of the error area and the maximum and average end-of-line deviations for visual inspection.

Abstract: The present invention is directed to an optical proximity correction driven hierarchy. A method for constructing a hierarchy of optically independent structures for use in optical proximity correction of a circuit may include receiving an integrated circuit design, the design including geometric circuit elements for providing circuit functions of an integrated circuit. At least a portion of the integrated circuit design is exploded and geometric circuit elements of the exploded integrated circuit design are gathered into optically independent classes.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: An aerial image produced by a mask having transmissive portions is simulated by dividing the transmissive portions of the mask into primitive elements, obtaining a response for each of the primitive elements, and then simulating the aerial image by combining the responses over all of the primitive elements.