Abstract: A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue. Requests that are allowed to pass a posted memory write are written to a separate second queue. Requests at the head of these queues receiving a RETRY response or failing to execute completely are removed from the queue and stored in a Retry List. Requests execute depending on which one of them wins control of the destination bus. The posted memory writes queue and any request not allowed to pass a posted memory write are blocked from executing if there is a location in the Retry List occupied by a posted memory write.

Abstract: An improved SRTS clock recovery system of a network node that adjusts the range of a received source RTS sample and a locally generated destination RTS sample to compensate for inherent characteristics of a network system. In addition, the improved system extends the range of the RTS samples to properly interpret large phase differences between a source node clock and transmit clock generated by the network node. This novel technique for interpreting source and destination RTS samples enables the improved network node to accurately recover a source clock frequency from a network transmission in a highly stressed network system. Specifically, the SRTS clock recovery system includes an RTS sample interpreter having a slope determinator for determining the expected average change in source and destination RTS samples over time.

Abstract: A destination station receives from a network a data packet that is transmitted as a plurality of cells and separately encodes each of the received cells, to produce associated, individual c-bit partial CRC remainders, where c is the number of bits in the CRC remainder associated with the packet. These partial CRC remainders correspond to the respective contributions that the cells make to the packet CRC pattern. The encoder appends the partial CRC remainders to the cells, and the station then stores them in an associated memory and links the individual cells to previously stored cells from the same packet with pointers. Once all the cells of a packet are encoded and stored, the destination station retrieves appended partial CRC remainders from the memory, and provides the remainders to a partial CRC encoder. The encoder manipulates the partial remainders and produces a packet CRC remainder.

Abstract: The classifier device disclosed herein analyzes message headers of the type which comprise a sequence of bit groups presented successively. The device employs a read/write memory for storing at a multiplicity of addresses, an alterable parse graph of instructions. The parse graph instructions include node instructions which comprise opcodes in association with respective next address characterizing data and terminator instructions which comprise identifying data for previously characterized header types. A logical processor responds to a node instruction read from memory either by initiating another memory read at a next address which, given the current state of the processor, is determinable from the current node instruction and the current header bit group or by outputting data indicating recognition failure if no next address is determinable. The logical processor responds to a terminator instruction by outputting respective header identifying data.

Abstract: One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68).

Abstract: A special instruction processor that connects to a central processing unit in a data processing system. The central processing unit processes a number of instructions. Instructions involving operands first retrieve the operands from memory, from general purpose registers in the central processor or the instruction stream. These operands are transferred to the special instruction processor. If the instruction is one of a predetermined set of instructions that is executed by the special instruction processor, the special instruction processor will, upon receiving the operands, generate an overriding signal that alters the operation of the central processor unit by inhibiting its processing of the operands. Instead, the special instruction processor unit, that is specifically designed to perform the operations efficiently, computes a result.