Abstract: Using classic Fast Fourier Transform (FFT) rules, a radix-12 FFT is composed of a first tier of 2 multiplierless radix-6 transformers followed by multiplierless radix-2 transformers, or by its transpose configuration. Complex data are represented in a 1, W.sub.3 coordinate system rather than in a classic 1,j coordinate system. The only multiplicative scaler in the complex twiddle factors is the reciprocal of the square root of 3 which appears six times and which by conversion to canonical signed digit code, can be accurately expressed by 5 adds. As a consequence the complex twiddle factor multipliers and ancillary address reduce to a total of 144 real adds required to perform the entire complex 12-point FFT.

Abstract: The one-bit sigma-delta modulator with improved signal stability disclosed herein includes, in order, a first anti-aliasing filter (20), a chopper (22), a second anti-aliasing filter (30), and a one-bit modulator (32). The chopper (22) and one-bit modulator (32) are driven by a clock generator (38). The chopper (22) is introduced to provide a carrier upon which the signal may ride, thereby eliminating dc stability problems. The first anti-aliasing filter (20) eliminates aliasing from the chopper (22), and the second anti-aliasing filter (30) eliminates aliasing from the one-bit modulator (32). The second anti-aliasing filter (30) may be eliminated if the frequency of the chopper (22) is an exact integer submultiple of the sampling frequency of the one-bit modulator (32). This invention may drive a decimation filter (36), also driven by the clock generator (38), to provide a low cost analog-to-digital converter.

Abstract: A modular, arrayable, FFT processor for performing a preselected N-point FFT algorithms. The processor uses an input memory to receive and store data from a plurality of signal-input lines, and to store intermediate butterfly results. At least one Direct Fourier Transformation (DFT) element selectively performs R-point direct Fourier transformations on the stored data according to a the FFT algorithm. Arithmetic logic elements connected in series with the DFT stage perform required phase adjustment multiplications and accumulate complex data and multiplication products for transformation summations. Accumulated products and summations are transferred to the input memory for storage as intermediate butterfly results, or to an output memory for transfer to a plurality of output lines. At least one adjusted twiddle-factor storage element provides phase adjusting twiddle-factor coefficients for implementation of the FFT algorithm.

Abstract: A frequency-domain Fast Fourier Transform windowing device includes a plurality of input lines, each of which is coupled to a corresponding frequency bin output line of an FFT; and a memory. The memory includes address input ports connected to the input lines and an output line. The memory reads out onto the output line values read out from the locations in the memory corresponding to signals received at the address input ports. The memory has stored in it values corresponding to the coneolution of samples on several of the input lines and the corresponding predetermined weighting coefficients.

Abstract: An FFT building block useful in building FFT arrays includes a discrete-Fourier-transform device (DFT) having a plurality of DFT input lines, and a plurality of multipliers. Each multiplier has a multiplier-input line and a multiplier-output line. The multiplier-output line of each multiplier is connected to a corresponding DFT input line. Each multiplier implements distributed arithmetic to produce at the multiplier output a value corresponding to a combination of a value on the multiplier-input line and a predetermined multiplier coefficient.

Abstract: A nonlinear adaptive filter has an input and an output, and includes an adjustable linear filter and nonlinear filter connected serially between the input and output. The parameters for the adjustable linear filter are derived from signals on the adaptive filter output and from signals on the adaptive filter input. Preferably, the adjustable linear filter is coupled between the adaptive filter input and the nonlinear filter. A parameter computer for adjusting the parameters of the adjustable linear filter includes an input coupled to the output of the nonlinear filter, a processor for processing a signal received from the output of the nonlinear filter, and apparatus for applying the processed output signal to the parameters of the adjustable linear filter. A linear filter for shaping the spectrum of a signal received from the output of the nonlinear filter is preferably coupled between the nonlinear filter output and the parameter computer.

Abstract: A high-speed distributed-arithmetic realization of a second-order normal-form digital filter includes a filter input, a filter output, and a memory. The memory has a first input, a second input, and a third input. The first memory input is connected to the filter input. The memory also has a first output, a second output, and a third output. The digital filter additionally includes a first adder having an input connected to the first memory output, and having its output connected to the filter output. A second adder has an input connected to the second memory output, and has its output connected to the second memory input. A third adder has an input connected to the third memory output and has its output connected to the third memory input.

Abstract: A signal processor suitable for use as a discrete-time or sampled-data analog filter can be implemented by using only a few of the coefficient multipliers of a typical analog finite-impulse-response (FIR) filter, and expressing each coefficient multiplier as a multibit digital word. Each bit of the multibit word is formulated as a tap weight coupled to a delay element of an input-delay line. Factor elements are coupled to the outputs of the bit-tap-weights to multiply the outputs of those bit-tap-weights by factors representative of the significance of the bit represented by that weight. Bit-tap weight outputs from tabs that were lens delayed on the input line are delayed upon output so the outputs of all the bit-tap weights associated with a single multibit word are combined together to form a single output. The output signal is interpolated in an interpolator to recover the information lost by omitting some of the coefficient multipliers.

Abstract: A signal processor is for receiving an input signal y. The input signal y has in it a signal x and has a conditional density function, given that the signal x is present, p(y.vertline.x). The signal processor includes a memory for storing the amplitude-density-function of the signal x, p(x). The memory is coupled to the processor input so that the memory is addressed by the input signal y. An amplitude-density-function generator is coupled to the processor input and to the memory generates the product of the conditional density function p(y.vertline.x) and the density function p(x). The processor of the invention also includes apparatus for detecting the peak of that product.

Abstract: A method and apparatus for multiplying two digital pairings representing complex numbers is described. The method includes preloading a memory with contents based on the second complex combination and the basis vector, and repeatedly addressing the memory based on the first complex combination taken L bits at a time in order to accumulate a complex product combination. The complex multiplication apparatus is preferably constructed as high speed circuitry on a gallium arsenide integrated circuit chip.

Abstract: A signal processing device for the correction of signal amplitude distortion occurring in a plurality of signalling channels such as obtained from a detector array in which each detector has a different non-uniform response. Compensatory amplitude adjustment is made to each sampled signal in accordance with the statistical deviation of the signal from a preselected statistical model. A signal sampling device employs each sampled signal as a write-address for generating a statistical amplitude distribution function. Inverse distribution function means, responsive to addressing by the distribution function, provides an output signal of compensatorily modified amplitude for each signal sample.

Abstract: A charge-transfer-device (CTD) transversal filter which makes use of tap-weight-adjustment circuitry for removing effects of charge-transfer inefficiency (CTI) and fixed-pattern noise (FPN). The tap weights are adjusted by measuring the response of the CTD-transversal filter to an isolated pulse input and to a zero-frequency input. The results of the measurements and reference-filter coefficients are used by the tap-weight-adjustment circuitry in order to set tap weights for the CTD-transversal filter. The tap-weight-adjustment circuitry allows the frequency response of the CTD transversal filter to be accurately tailored even though the CTD filter suffers imperfections due to CTI and FPN.

Abstract: A transversal adaptive filter with a tap weight computer having a respective first and second input responsively coupled to a respective output and input of the filter, and including spectrum shaping means. The spectrum shaping means comprises matched or like preselected bandpass means interposed at the inputs of the tap weight computer.

Abstract: A digital data processor adapted to be responsive to an applied signal input (x.sub.n) for generating an output signal indicative of a preselected function of the signal input, and comprising signal sampling memory means adapted to be responsive to an alternate one of the applied input signal and a clocked counter output as a read/write-address for generating a statistical amplitude density function d(x) representing the number of occurrences of an amplitude of a sampled input x. Digital attenuating means is interposed between a read-out and read-in of said memory means during sampling intervals in which said memory means is responsive to said clocked counter output for low-pass filtering the amplitude density function as to be dependent of the size of the sampled population of the sampled signal (x.sub.n).

Abstract: A multiplexer for allowing multi-octave processing of sampled data by means of a common single-octave data processor. Sampled data is preselectively delayed, corresponding to delay-coding thereof, and a multiplex switch samples the progressively delayed delay-coded data at progressively reduced data sampling rates, corresponding to lower octaves of interest. In this way the several octaves of data are interleaved or time-multiplexed. Similar multiplexing within the single-octave data processor corresponds to frequency multiplexing of the time-multiplexed multi-octave data, whereby the single bandwidth limit processor may handle such multiple-octave data.

Abstract: A four-port digital complex multiplier useful for FFT butterfly arithmetic units and in which ROM's are employed as square function look-up tables. Each of the four ports is responsive to a respective one of the component values of two complex numbers. The square-function look-up memories are responsive to various ones of the input ports and cooperate with quarter-square-multipliers to provide component complex products. An output subtractor and an output summer, responsive to mutually exclusive pairs of the quarter-square multipliers, provide a respective real and imaginary component of the product of the two complex numbers.

Abstract: A device for the correction of signal distortion occurring in a signalling channel. Compensatory amplitude adjustment is made to a sampled signal in accordance with the statistical deviation of the signal from a preselected statistical model. Signal sampling means employs the sampled signal as a write-address for generating a statistical amplitude distribution function. Inverse distribution function means, responsive to addressing by the distribution function, provides an output signal of compensatorily modified amplitude.

Abstract: A fully-parallel digital arithmetic device for obtaining the square, C.sup.2, of a value, C, via parts of the value C and involving a reduction in memory requirements. Three square function ROM's are employed, one responsive to the most significant-bits half of a parallel input, the second ROM responsive to the least-significant bits half of the parallel input, and the third one responsive to the sum of said most significant bits and least-significant bits. The outputs of the square function ROM's are then combined and scaled to effect a square by parts of the applied input value, C. A pair of such arithmetic devices may be advantageously combined to economically effect the product AB of two values, A and B, in the manner of a quarter square multiplier.

Abstract: An improved organization for a FFT analyzer (or periodic function analyzer) having a reduced computing complexity. A modified organization comprises a simplified butterfly arithmetic unit in which the usual two coefficient registers or memories are required. By utilizing the registers as sources of a respective sum of and difference between sets of phase-shifted cosine values, the mechanization of the complex multiplier for such arithmetic butterfly unit in microcircuit or "chip" form may be further simplified to two controllable accumlators controlled by an exclusive-NOR gate logic system responsive to the states of the complex sampled inputs of a sampled signal epoch of interest. In this way, a more efficient and higher speed device is provided for the multiplication of complex variables.

Abstract: Signalling means for enhancing the performance of automatic fingerprint identification systems by reducing system response to non-fingerprint-like regions within an image field pattern of interest. A two dimensional generalized sequency analyzer, such as a fast Fourier transform machine, responsive to a binary coded image signal identifies discrete frequency terms occurring within a selected bandwidth corresponding to a spatial frequency region of interest, associated with a fingerprint image. Logic means, responsive to the sequency analyzer, further identifies the relative energy levels of the bandwidth-limited spectral content of the binary coded image signal to signal the identity of a non-fingerprint-like region within the scanned image.