Abstract: A polycrystalline silicon GOLDD TFT with a gate (10) overlying its channel (11) is fabricated by using the gate (10) as a mask during a first dopant implantation step. Spacers (13, 14) are then formed adjacent to the gate (10), which comprise portions of a thin metallic layer (19) which are defined by fillets (17) in an etching process. The spacers and gate are then used as a mask for doping source and drain regions, thereby providing a self-aligned fabrication technique.

Abstract: A thin film transistor (100) is mounted on a substrate (102), which is covered by a semiconductor layer (120). The semiconductor layer (120) has a first doped region (121) and a second doped region (122) with an undoped region (123) in between. In addition, the semiconductor layer (120) has a first further doped region (125) and a second further doped region (126) forming the source and drain of the thin film transistor (100) and being more heavily doped than the first doped region (121) and the second doped region (122). A part of the semiconductor layer (120) is covered by an oxide layer (140), which carries a conductive gate (104) over the undoped region (130) and a first spacer (111) and second spacer (112) over the first doped region (121) and the second doped region (122) respectively.