Patents by Inventor Stanley E. Groves
Stanley E. Groves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5204957Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.Type: GrantFiled: September 30, 1992Date of Patent: April 20, 1993Assignee: MotorolaInventors: Brian F. Wilkie, Vernon B. Goler, Stanley E. Groves, John J. Vaglica
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Patent number: 5129078Abstract: A system comprises a service processor and a plurality of operating units dependent on the service processor. The service processor responds to service requests from the operating units and services the operating units one at a time. A scheduler is responsible for assigning priority to the operating units and determining the order in which the service requests are handled. A register contains a value indicative of the operating unit currently being serviced and is under control of the scheduler. According to one aspect of the present invention the register is also under control of the service processor itself. Another register, under control of the service processor, is coupled to the scheduler to generate service requests thereto independent of the operating units. A memory addressable by the service processor stores data. The service processor is capable of generating addresses for the memory derived from the contents of the register indicative of the operating unit currently being serviced.Type: GrantFiled: August 19, 1988Date of Patent: July 7, 1992Inventors: Stanley E. Groves, Vernon B. Goler, Gary L. Miller, Mario Nemirovsky, Robert S. Porter
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Patent number: 4958277Abstract: A serial peripheral interface achieves compatibility with devices having previous such interfaces while singificantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.Type: GrantFiled: April 21, 1989Date of Patent: September 18, 1990Assignee: Motorola, Inc.Inventors: Susan C. Hill, Joseph Jelemensky, Mark R. Heene, Stanley E. Groves, Daniel N. DeBrito
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Patent number: 4952367Abstract: A timer system comprises a plurality of timer channels serviced by a single service processor. Each of the timer channels is capable of both input (capture) and output (match) functions. The microprogrammed service processor is responsible for configuring each of the channels for their intended uses and for responding to service requests generated by the channels in response to the occurrence of timer events. Features of the timer channels include the ability to continuously execute capture functions without generating service requests, the ability to execute a single capture function and service request and protect the captured value from being overwritten until the service request has been responded to and the ability to combine match and capture functions in such a way as to place a time-out window on the capture event.Type: GrantFiled: August 19, 1988Date of Patent: August 28, 1990Assignee: Motorola, Inc.Inventors: Robert S. Porter, Vernon Goler, Gary L. Miller, Stanley E. Groves, Mario Nemirovsky
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Patent number: 4942522Abstract: A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.Type: GrantFiled: August 19, 1988Date of Patent: July 17, 1990Assignee: Motorola, Inc.Inventors: Brian F. Wilkie, Vernon B. Goler, Stanley E. Groves, John J. Vaglica
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Patent number: 4926319Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.Type: GrantFiled: August 19, 1988Date of Patent: May 15, 1990Assignee: Motorola Inc.Inventors: Brian F. Wilkie, Vernon B. Goler, Stanley E. Groves, John J. Vaglica
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Patent number: 4758950Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.Type: GrantFiled: April 13, 1987Date of Patent: July 19, 1988Assignee: Motorola, Inc.Inventors: Michael Cruess, Donald L. Tietjen, Van B. Shahan, Stanley E. Groves
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Patent number: 4365210Abstract: A data and clock recovery system for capturing and processing serial data of a type wherein data bits of an unknown format are interleaved with clock bits utilizes a phase lock loop capable of being operated in a capture mode or a tracking mode. The data stream is compared with an internally generated reference signal, and error pulses having widths proportional to the phase error are generated. In the capture mode, these error pulses are differentially processed to produce a control voltage which varies the frequency of a VCO which in turn alters the reference frequency. In the tracking mode, phase error pulses of fixed widths are processed only if the data bits occur in fixed windows. Differential amplifying means provide adjustable gain control of the error pulses. Means are provided for digitally controlling the loop's dynamic response when switching between the capture and tracking modes.Type: GrantFiled: June 26, 1980Date of Patent: December 21, 1982Assignee: Motorola, Inc.Inventors: Wayne D. Harrington, Stanley E. Groves
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Patent number: 4361876Abstract: A single-chip microcomputer includes a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a control and status register (46), one bit (WU) of which may be utilized, when the microcomputer is connected in a distributed processing system having a shared serial communication line, to indicate that the CPU wishes to ignore a message not of interest to it. When the serial communication line again becomes free, the WU control bit is reset, enabling the CPU to intercept a new message of interest.Type: GrantFiled: September 5, 1978Date of Patent: November 30, 1982Assignee: Motorola, Inc.Inventor: Stanley E. Groves
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Patent number: 4346452Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic is capable of handling serial communications in either the NRZ or Manchester (biphase) format. The result is more versatile and more reliable serial communications.Type: GrantFiled: September 5, 1978Date of Patent: August 24, 1982Assignee: Motorola, Inc.Inventor: Stanley E. Groves
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Patent number: 4317053Abstract: In a high speed synchronizing circuit, the rising edge of an asynchronous input signal is used to set an input RS flip-flop. First and second latch registers monitor the input RS flip-flop. Each latch register generates a reset signal before a change in the logic level of the system clock for resetting the input RS flip-flop. The reset pulses are very narrow which enables the RS flip-flop to be quickly conditioned to receive the next asynchronous signal.Type: GrantFiled: December 5, 1979Date of Patent: February 23, 1982Assignee: Motorola, Inc.Inventors: Pern Shaw, Stanley E. Groves
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Patent number: 4236204Abstract: An instruction set modifier register, comprising one or more bistable latches which are loadable under program control, is provided for use in a processor in conjunction with an instruction register. An instruction decoding circuit and an instruction execution control logic circuit, responsive to both the instruction register and the instruction set modifier register, generate a first set of control signal combinations corresponding to a first instruction set when the instruction set modifier register is in a first state and generate a second set of control signal combinations corresponding to a second instruction set when the instruction set modifier register is in a second state. The processor is thus able to execute more than one set of instructions, utilizing the same instruction decoding circuitry and instruction execution control logic circuitry.Type: GrantFiled: March 13, 1978Date of Patent: November 25, 1980Assignee: Motorola, Inc.Inventor: Stanley E. Groves
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Patent number: 4222116Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14).The serial I/O communication logic includes a shift register (RBA-RBH, FIG. 8J) to separate the data and clock signals in a Manchester-encoded data stream. The Manchester encoding is adaptable to any data rate simply by changing the frequency of a high speed clock associated with the shift register.Type: GrantFiled: September 5, 1978Date of Patent: September 9, 1980Assignee: Motorola, Inc.Inventor: Stanley E. Groves
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Patent number: 4161787Abstract: A programmable timer module (PTM) is provided as a component of a microprocessor system in order to generate and measure varying time intervals under program control. The programmable timer module includes, in one embodiment, three independent 16-bit timers. Each timer includes a 16-bit counter and a 16-bit latch. The programmable timer module also includes an 8-bit status register and an 8-bit control register each of which may be coupled to an 8-bit bidirectional data bus of a microprocessor system. Selection circuitry is provided which permits the microprocessor to select either the control register or the status register. Information can be written into the control register; the operation is effected by means of read/write circuitry and a read/write input. Any one of the three timers can also be selected by means of the selection circuitry, and a 16-bit number can be written into the selected 16-bit latch.Type: GrantFiled: November 4, 1977Date of Patent: July 17, 1979Assignee: Motorola, Inc.Inventors: Stanley E. Groves, Gene A. Schriber, Brian M. Spinks, Richard M. Baker, Thomas C. Daly, Rodney J. Means