Patents by Inventor Stanley E. Swirhun
Stanley E. Swirhun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7053415Abstract: A monolithically integrated VCSEL and photodetector, and a method of manufacturing the same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons which are not initially absorbed back into the photodetector. The transmit and receive pairs are packaged into a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.Type: GrantFiled: June 4, 2003Date of Patent: May 30, 2006Assignee: Optical Communication Products, Inc.Inventors: Stanley E. Swirhun, Jeffrey W. Scott
-
Patent number: 6835992Abstract: A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds the layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where the photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons back into the photodetector not initially absorbed. The transmit and receive pairs are packaged in a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.Type: GrantFiled: January 18, 2000Date of Patent: December 28, 2004Assignee: Optical Communication Products, Inc.Inventors: Stanley E. Swirhun, Jeffrey W. Scott
-
Publication number: 20030228716Abstract: A monolithically integrated VCSEL and photodetector, and a method of manufacturing the same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons which are not initially absorbed back into the photodetector. The transmit and receive pairs are packaged into a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.Type: ApplicationFiled: June 4, 2003Publication date: December 11, 2003Inventors: Stanley E. Swirhun, Jeffrey W. Scott
-
Patent number: 6001664Abstract: A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds the layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where the photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons back into the photodetector not initially absorbed. The transmit and receive pairs are packaged in a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.Type: GrantFiled: February 21, 1997Date of Patent: December 14, 1999Assignee: Cielo Communications, Inc.Inventors: Stanley E. Swirhun, Jeffrey W. Scott
-
Patent number: 5677554Abstract: A HIGFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only over the active area of the FET and a photo resist covering on the gate metal. The wafer, including the area covered by the photo resist, is covered with the dielectric layer. The photo resist layer is removed along with the dielectric layer from over the gate metal. Another layer of gate metal is formed on the preexisting gate metal including a gate pad on part of the remaining dielectric layer.Type: GrantFiled: May 5, 1995Date of Patent: October 14, 1997Assignee: Honeywell Inc.Inventor: Stanley E. Swirhun
-
Patent number: 5633183Abstract: A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.Type: GrantFiled: July 12, 1995Date of Patent: May 27, 1997Assignee: Honeywell Inc.Inventor: Stanley E. Swirhun
-
Patent number: 5631988Abstract: An optical interconnect is disclosed that couples multiple optical fibers to an array of optoelectronic devices. The interconnect includes a multiple optical fiber connector and an optoelectronic board. The multiple fiber connector can be mechanically attached to or detached from the board.Type: GrantFiled: June 21, 1996Date of Patent: May 20, 1997Assignee: Vixel CorporationInventors: Stanley E. Swirhun, Toshi K. Uchida
-
Patent number: 5625480Abstract: Simple and efficient electronic circuits and methods are disclosed for better use of parallel optical interconnect system transmitting a plurality of dc NRZ data and an independent clock signal. The present invention dynamically compensates for the effects of the substrate temperature and aging behavior of the light emitters at both the transmitter and the receiver. In addition, a special arrangement of light emitters is used to reduce or avoid skew problems.Type: GrantFiled: May 24, 1996Date of Patent: April 29, 1997Inventors: Stanley E. Swirhun, Iain R. Mactaggart
-
Patent number: 5606572Abstract: Photodiodes are integrally formed with vertical cavity surface emitting lasers (VCSELs) and superluminescent light emitting diodes (SLEDs) for monitoring optical radiation intensities. In different embodiments, the photodiode is epitaxially formed within a mirror of a VCSEL, non-epitaxially formed on top of a VCSEL, non-epitaxially formed on side of a VCSEL, or formed on the substrate on the side opposite the VCSEL. A lateral injection vertical cavity surface emitting laser is also disclosed for integration with a lateral PIN photodiode. A photodiode having the same epitaxial layers as a VCSEL is also integrally formed alongside of the VCSEL. Similar devices using SLEDs are also disclosed.Type: GrantFiled: March 24, 1994Date of Patent: February 25, 1997Assignee: Vixel CorporationInventors: Stanley E. Swirhun, William E. Quinn
-
Patent number: 5577064Abstract: Photodiodes are integrally formed with vertical cavity surface emitting lasers (VCSELs) and superluminescent light emitting diodes (SLEDs) for monitoring optical radiation intensities. In different embodiments, the photodiode is epitaxially formed within a mirror of a VCSEL, non-epitaxially formed on top of a VCSEL, non-epitaxially formed on side of a VCSEL, or formed on the substrate on the side opposite the VCSEL. A lateral injection vertical cavity surface emitting laser is also disclosed for integration with a lateral PIN photodiode. A photodiode having the same epitaxial layers as a VCSEL is also integrally formed alongside of the VCSEL. Similar devices using SLEDs are also disclosed.Type: GrantFiled: October 18, 1995Date of Patent: November 19, 1996Assignee: Vixel CorporationInventors: Stanley E. Swirhun, William E. Quinn
-
Patent number: 5570697Abstract: An on-airway breath-by-breath oxygen sensor is described which has the necessary low weight, fast response and high precision required for oxygen consumption measurement. A vertical-cavity surface-emitting laser (VCSEL) is continuously tuned to emit light at the resonance of oxygen, or more generally, the molecular species of interest. The light beam is directed through a sample containing the molecular species of interest onto a detector. The amount of light absorbed is approximately proportional to the concentration of the molecular species of interest in the sample.Type: GrantFiled: July 15, 1994Date of Patent: November 5, 1996Assignee: Vixel CorporationInventors: Stephen D. Walker, Jack L. Jewell, Greg R. Olbright, Stanley E. Swirhun
-
Patent number: 5521736Abstract: Simple and efficient electronic circuits and methods are disclosed for better use of parallel optical interconnect system transmitting a plurality of dc NRZ data and an independent clock signal. The present invention dynamically compensates for the effects of the substrate temperature and aging behavior of the light emitters at both the transmitter and the receiver. In addition, a special arrangement of light emitters is used to reduce or avoid skew problems.Type: GrantFiled: September 29, 1994Date of Patent: May 28, 1996Assignee: Vixel CorporationInventors: Stanley E. Swirhun, Iain R. Mactaggart
-
Patent number: 5461244Abstract: A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.Type: GrantFiled: January 3, 1994Date of Patent: October 24, 1995Assignee: Honeywell Inc.Inventor: Stanley E. Swirhun
-
Patent number: 5455183Abstract: A HIGFET having a gate with a pad which is isolated from the FET heterostructure wafer by a dielectric layer to minimize leakage current between the gate and the wafer. The method of production of this device involves application of the gate metal only over the active area of the FET and a photo resist covering on the gate metal. The wafer, including the area covered by the photo resist, is covered with the dielectric layer. The photo resist layer is removed along with the dielectric layer from over the gate metal. Another layer of gate metal is formed on the preexisting gate metal including a gate pad on part of the remaining dielectric layer.Type: GrantFiled: January 3, 1994Date of Patent: October 3, 1995Assignee: Honeywell Inc.Inventor: Stanley E. Swirhun
-
Patent number: 5420954Abstract: An optical interconnect is disclosed that couples multiple optical fibers to an array of optoelectronic devices. The interconnect includes a multiple optical fiber connector and an optoelectronic board. The multiple fiber connector can be mechanically attached to or detached from the board.Type: GrantFiled: May 24, 1993Date of Patent: May 30, 1995Assignee: Photonics Research IncorporatedInventors: Stanley E. Swirhun, Toshi K. Uchida
-
Patent number: 5412680Abstract: This invention discloses vertical cavity surface emitting lasers (VCSELs) formed to emit optical radiation that has a controlled direction of polarization. In one embodiment, a VCSEL has an active region that contains at least one strained semiconductor layer which has a preferred direction of electrical conductivity due to the strain. As a result, the optical radiation emitted from the VCSEL has a direction of polarization that is parallel to the preferred direction of conductivity. In another embodiment, a VCSEL has an elongated active region, and the direction of polarization of the radiation emitted from the VCSEL is parallel to a longitudinal axis of the active region. The invention also discloses a VCSEL array comprising vertical cavity surface emitting lasers having elongated active regions. By forming the elongated active regions parallel to each other, the array emits optical radiation having parallel polarization.Type: GrantFiled: March 18, 1994Date of Patent: May 2, 1995Assignee: Photonics Research IncorporatedInventors: Stanley E. Swirhun, Thomas J. O'Neill, Jr.
-
Patent number: 5159346Abstract: A voltage controlled oscillator (VCO 10) is disclosed in a "ring" configuration using two FETs. Two isolated voltage control terminals provide increased tuning bandwidth. The design uses an active feedback topology resulting in greater device size for higher output power and circuit Q.Type: GrantFiled: June 10, 1991Date of Patent: October 27, 1992Assignee: Alliant Techsystems Inc.Inventors: Donald N. Bosch, James B. Beyer, Robert L. Cravens, Stanley E. Swirhun