Abstract: The present invention related to monitoring internet traffic for illegal Intellectual Property transfers, viruses, criminal and other illegal activities. It also assists the Internet search engine providers in generating fast and accurate responses to Internet Recipient (IR) database queries. A massively parallel network of processing units residing within a single programmable ASIC device assures speeds in excess of 100 Gigabits/second.

Abstract: The present invention related to monitoring internet traffic for illegal Intellectual Property transfers, viruses, criminal and other illegal activities. It also assists the Internet search engine providers in generating fast and accurate responses to Internet Recipient (IR) database queries. A massively parallel network of processing units residing within a single programmable ASIC device assures speeds in excess of 100 Gigabits/second.

Abstract: A method and apparatus for development and concurrent verification of digital designs including a combination of a microprocessor and discrete logic design blocks. The hardware/software design development and co-verification processing of digital designs is accelerated by placing the microprocessor in an FPGA device and logic circuits in an HDL simulator. The microprocessor and logic circuits are connected via a common bus and synchronization of both environments is achieved by using a simulator clock exclusively when both microprocessor and logic simulator need to communicate with each other. The system and method of the present invention provides a unique arrangement of a processor clocking scheme. An essential part of the invention is a clock switch responsive to the areas of RAM a processor is addressing and accordingly switching a clock signal to the processor from either a hardware clock generator or a software simulator.

Abstract: A method and system for accelerating software simulator operation with the aid of reprogrammable hardware such as Field Programmable Gate Array devices (FPGA). The method and system aid in emulation and prototyping of Application Specific Integrated Circuits (ASIC) digital circuit designs by means of reprogrammable devices. The system includes a design verification manager and software program that includes subroutines of finding clock sources, finding synchronous primitives that are receiving clock signals from the clock sources, and a subroutine for inserting edge detector circuits between such clock sources and synchronous primitives. This new method allows eliminating of clock timing issues by applying basic design clocks to the clock enable instead of clock trigger inputs and generating and applying to clock trigger inputs a new clock that is automatically delayed in respect to all other clocks in the design.