Abstract: The present disclosure relates to a digital asset synchronization system that provides improved local and remote synchronization of digital assets. In particular, the digital asset synchronization system manages digital assets by separating each digital asset into multiple components stored as a set of distributed individual files. Employing individual components for a digital asset rather than single monolithic file enables the digital asset synchronization system to provide safe concurrent access to the digital asset from multiple applications on the same device and across different devices. In addition, using components for a digital asset provides the digital asset synchronization system with the ability to efficiently store and synchronize multiple versions of the digital asset, both locally and remotely.

Abstract: An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.

Abstract: In an apparatus and method for reducing current leakage in a phase locked loop (PLL), a pair of resistive divider circuit is coupled to receive a pair of differential input signals and provide a pair of differential output signals. A timing control circuit controls a pair of switches, the pair of switches being operable to conduct the pair of differential output signals in response to at least one signal of the pair of differential input signals being present. An operational amplifier (OA) includes a pair of OA input terminals and an OA output terminal. The pair of OA input terminals is coupled to receive the pair of differential output signals conducted by the pair of switches. A feedback circuit is coupled between the OA output terminal and a first one of the pair of OA input terminals. The pair of switches is disabled by the timing control circuit to block a current leakage from the feedback circuit.

Abstract: An integrated circuit, a phase locked loop, a voltage tune probe and a method of screening an integrated circuit employing a phase locked loop thereof. In one embodiment, the integrated circuit includes: (1) an input/output port configured to provide an external interface lead for the integrated circuit, (2) a phase locked loop having a voltage tune line coupled to a voltage controlled oscillator and (3) a voltage tune probe having a first switch coupled to a second switch and a capacitor coupled therebetween. The first switch is coupled to the voltage tune line and the second switch is coupled to the input/output port. The switches provide a bidirectional connection between the external interface lead and the voltage tune line.

Abstract: In an apparatus and method for reducing current leakage in a phase locked loop (PLL), a pair of resistive divider circuit is coupled to receive a pair of differential input signals and provide a pair of differential output signals. A timing control circuit controls a pair of switches, the pair of switches being operable to conduct the pair of differential output signals in response to at least one signal of the pair of differential input signals being present. An operational amplifier (OA) includes a pair of OA input terminals and an OA output terminal. The pair of OA input terminals is coupled to receive the pair of differential output signals conducted by the pair of switches. A feedback circuit is coupled between the OA output terminal and a first one of the pair of OA input terminals. The pair of switches is disabled by the timing control circuit to block a current leakage from the feedback circuit.

Abstract: An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.

Abstract: An integrated circuit, a phase locked loop, a voltage tune probe and a method of screening an integrated circuit employing a phase locked loop thereof. In one embodiment, the integrated circuit includes: (1) an input/output port configured to provide an external interface for the integrated circuit, (2) a phase locked loop having a voltage tune line coupled to a voltage controlled oscillator and (3) a voltage tune probe having a first switch coupled to a second switch and a capacitor coupled therebetween. The first switch is coupled to the voltage tune line and the second switch is coupled to the input/output port.

Abstract: A low noise multi-loop radio frequency synthesizer receives an input reference signal having a frequency fR, into a fine tune PLL and a coarse tune PLL. The fine tune PLL outputs a fine tune signal with a frequency fR?P, P beings an integer, while the coarse tune PLL outputs a coarse tune signal with frequency fR?A, where A is an integer. A translation PLL has a unity multiplication factor and is driven by the fine tune signal output. The frequency synthesizer has a Gilbert cell double balanced mixer coupled between the coarse tune and the translation PLLs, the Gilbert cell mixer combining the coarse tune signal and the output signal of the translation PLL and coupling the mixed signal into the translation PLL. The translation loop outputs a signal with a frequency proportional to the linear sum of the coarse tune signal and the fine tune signal.

Abstract: A method of improving the battery charge measurement range in a sigma delta converter associated with portable applications such as a cell phone is implemented by interruption of the sigma delta modulator measurement process and changing its reference voltage and measurement time to allow an integrated current to occur over a wider dynamic range.

Abstract: A phase locked loop with two zeros/two poles active compensation. The two poles and two zeros provide increased stability with capability for narrow bandwidth and the active component (such as operational amplifier) provides increased gain and higher noise immunity. Schematic diagrams of exemplary and preferred embodiments, design assumptions, and associated equations are disclosed. Other assumptions and equations are within the scope of the invention, provided the disclosed format for an open loop voltage transfer function for two zeros/two poles is maintained.

Abstract: A low noise multi-loop radio frequency synthesizer is disclosed for the read channel in a hard disk drive, and for RF wireless communications local oscillator applications. The frequency synthesizer receives an input reference signal having a frequency fR, into a fine tune phase locked loop and into a coarse tune phase locked loop. Driven by the input reference signal, the fine tune PLL outputs a fine tune signal with a frequency fR·P, where P is an integer, while the coarse tune PLL, also driven by the same input reference signal, outputs a coarse tune signal with a frequency fR·A, where A is an integer. A translation phase locked loop has a unity multiplication factor and is driven by the fine tune signal output.

Abstract: A system 400 and method 1400 are disclosed for a lock detection circuit of a phase locked loop used in a communications device. The lock detection circuit includes a cycle slip detector and a clock presence detector. The cycle slip detector receives a reference clock and a VCO feedback clock, and in response to the frequency difference between the reference clock and the VCO feedback clock that remains for a time period greater than the inverse of the frequency difference of the clocks, generates a no cycle slips alarm indication. The no cycle slips alarm status enables the lock detection circuit to provide an indication to the PLL, of the lock condition and whether a cycle slip has occurred. The clock presence detector receives the reference clock and the VCO feedback clock, and in response to determining whether the reference clock or the VCO feedback clock is missing for a time greater than a predetermined count of either remaining clock, generate a no VCO alarm and a no REF alarm indication.

Abstract: An oscillator controls the frequency of an output clock signal in response to detecting an error in the frequency of an input clock signal. The oscillator includes an inverter operable to generate a voltage signal and a resonator coupled to the inverter operable to introduce a phase shift in the voltage signal. The oscillator also includes a variable resistor positioned across a feedback path of the inverter and operable to introduce a further phase shift in the voltage signal in response to the detected error. The resonator is further operable to adjust the frequency of the voltage signal in response to the introduced further phase shift. The voltage signal is used as the output clock signal.

Abstract: An oscillator controls the frequency of an output clock signal in response to detecting an error in the frequency of an input clock signal. The oscillator includes an inverter operable to generate a voltage signal and a resonator coupled to the inverter operable to introduce a phase shift in the voltage signal. The oscillator also includes a variable resistor positioned across a feedback path of the inverter and operable to introduce a further phase shift in the voltage signal in response to the detected error. The resonator is further operable to adjust the frequency of the voltage signal in response to the introduced further phase shift. The voltage signal is used as the output clock signal.

Abstract: A circuit (14) for aiding proper frequency lock in a phase locked loop (12) includes a phase detector (40) adapted for receiving an input signal and an oscillator output signal from the phase locked loop (12) and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal. An up cycle slip detector (42a) receives the up pulse width modulated cycle slip signal and generates an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal. A down cycle slip detector (42b) receives the down pulse width modulated cycle slip signal and generates a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal. A phase correction circuit (41, 43) is provided for generating a steering signal in response to the up and down cycle slip signals.

Abstract: An improved ring oscillator (10, 70) includes a first, second and third current starved inverters (12, 14, 16) coupled in a ring, a first fast inverter (40) coupled between the second and third current starved inverters (14, 16), and a second fast inverter (45) coupled between the third and first current starved inverters (14, 16). An output buffer (30) coupled to the ring provides an output periodic waveform.