Patents by Inventor Stanley J. Kopec, Jr.

Stanley J. Kopec, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6034541
    Abstract: A programmable interconnect circuit includes multiple input/output cells, each corresponding to an input/output pin, and a global routing resource for routing signals received at the input pins to be output as output signals at output and bi-directional pins. The signals routed in the global routing resource can include multiplexer control signals, clock signals and output enable signals for controlling dynamic signal switching. The global routing resource allows high static routability.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: March 7, 2000
    Assignee: Lattice Semiconductor Corporation
    Inventors: Stanley J. Kopec, Jr., Cheng-Yuan Michael Wang, Jerome Connelly Farmer, Cyrus Y. Tsui
  • Patent number: 5111423
    Abstract: A programmable interface for a peripheral circuit card is provided. The card is intended for use with a particular computer bus architecture, and the interface can be customized by a user for a particular card design. Instead of designing a custom interface chip, the designer can program one or more programmable logic devices on the interface chip to interface with whatever devices are on the peripheral circuit card.
    Type: Grant
    Filed: July 21, 1988
    Date of Patent: May 5, 1992
    Assignee: Altera Corporation
    Inventors: Stanley J. Kopec, Jr., Yiu-Fai Chan, Robert F. Hartmann
  • Patent number: 4912342
    Abstract: A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
    Type: Grant
    Filed: September 14, 1989
    Date of Patent: March 27, 1990
    Assignee: Altera Corporation
    Inventors: Sau-Ching Wong, Hock-Chuen So, Stanley J. Kopec, Jr., Robert F. Hartmann
  • Patent number: 4871930
    Abstract: A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
    Type: Grant
    Filed: May 5, 1988
    Date of Patent: October 3, 1989
    Assignee: Altera Corporation
    Inventors: Sau-Ching Wong, Hock-Chuen So, Stanley J. Kopec, Jr., Robert F. Hartmann