Abstract: Digital character signals are split into at least two bit groups of different binary significance. The first and most significant of the bit groups is registered and periodically sampled for conversion in a resistor network to an analog format. The bits of the second, or least significant, bit group are utilized to produce a signal train including in a character time a number of pulses determined by the value of the second bit group and which pulses are approximately evenly located in the interval of the character. Each pulse of the train, as it occurs, momentarily augments the most significant bit group.One embodiment is shown in which the signal train produced is successive overflow carries from a high speed accumulation operation initially utilizing the least significant bit group and a starting character and thereafter using the least significant bit group and the immediately preceding accumulation sum.