Patents by Inventor Stanley Michael Filipiak

Stanley Michael Filipiak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6838354
    Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
  • Publication number: 20040119134
    Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
  • Patent number: 6475925
    Abstract: A method for forming a semiconductor device is disclosed in which a fluorinated silicon dioxide layer is formed over a semiconductor substrate. A first undoped silicon dioxide layer, with a thickness preferably less than approximately 50 nanometers, is then formed on the fluorinated silicon dioxide layer with a PECVD process wherein a power ratio of a high frequency power source of the PECVD reactor to a low frequency power source is preferably in a range of approximately 0.2:1 to 0.4:1. In one embodiment, a second undoped silicon dioxide layer may be formed prior to forming the fluorinated silicon layer. The second undoped silicon dioxide, the fluorinated silicon dioxide layer, and the first undoped silicon dioxide layer may be formed sequentially in the same plasma enhanced chemical vapor deposition process chamber during a single chamber evacuation cycle. The first undoped silicon dioxide layer is preferably characterized as having a refractive index greater than approximately 1.460.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: November 5, 2002
    Assignee: Motorola, Inc.
    Inventors: Gregor W. Braeckelmann, Stanley Michael Filipiak