Patents by Inventor Stanley Schuster

Stanley Schuster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DRAM HIERARCHICAL DATA PATH
    Publication number: 20080016277
    Abstract: A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard Matick, Stanley Schuster
  • INTERLOCKED SYNCHRONOUS PIPELINE CLOCK GATING
    Publication number: 20070294548
    Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
    Type: Application
    Filed: August 29, 2007
    Publication date: December 20, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPERATION
    Inventors: Hans JACOBSON, Prabhakar Kudva, Pradip Bose, Peter COOK, Stanley SCHUSTER
  • DRAM hierarchical data path
    Publication number: 20060233024
    Abstract: A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 19, 2006
    Inventors: Richard Matick, Stanley Schuster
  • Interlocked synchronous pipeline clock gating
    Publication number: 20060161795
    Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
    Type: Application
    Filed: March 14, 2006
    Publication date: July 20, 2006
    Inventors: Hans Jacobson, Prabhakar Kudva, Pradip Bose, Peter Cook, Stanley Schuster
  • Interlocked synchronous pipeline clock gating
    Publication number: 20060156046
    Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
    Type: Application
    Filed: March 14, 2006
    Publication date: July 13, 2006
    Inventors: Hans Jacobson, Prabhakar Kudva, Pradip Bose, Peter Cook, Stanley Schuster
  • Method and structure for short range leakage control in pipelined circuits
    Publication number: 20050083081
    Abstract: Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 21, 2005
    Inventors: Hans Jacobson, Pradip Bose, Alper Buyuktosunoglu, Peter Cook, Philip Emma, Prabhakar Kudva, Stanley Schuster