Abstract: A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.

Abstract: A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.

Abstract: Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.

Abstract: Initialization in multiple clock domains. A first die having a master initialization component generates initialization commands. A local initialization agent on the first die is coupled to receive the initialization commands. The local initialization agent manages initialization of one or more components on the first die. A remote initialization agent on a second die is coupled to receive the initialization commands. The remote initialization agent manages initialization of one or more components on the second die. The master initialization component receives acknowledgement messages from the local initialization agent and the remote initialization agent to manage conflicts and dependencies between the local initialization agent and the remote initialization agent and synchronizes events in multiple clock domains that share a reference clock signal by signaling in the reference clock domain.

Abstract: A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a protected region and a non protected region. The processor includes a protection engine to protect against active and passive attacks. The processor includes an encryption/decryption engine to protect against passive attacks. The protection engine includes bridge circuitry coupled between the memory controller and the one or more processing cores. The bridge circuitry is also coupled to the protection engine and the encryption/decryption engine. The bridge circuitry is to route first requests directed to the protected region to the protection engine and to route second requests directed to the non protected region to the encryption/decryption engine.

Abstract: Initialization in multiple clock domains. A first die having a master initialization component generates initialization commands. A local initialization agent on the first die is coupled to receive the initialization commands. The local initialization agent manages initialization of one or more components on the first die. A remote initialization agent on a second die is coupled to receive the initialization commands. The remote initialization agent manages initialization of one or more components on the second die. The master initialization component receives acknowledgement messages from the local initialization agent and the remote initialization agent to manage conflicts and dependencies between the local initialization agent and the remote initialization agent and synchronizes events in multiple clock domains that share a reference clock signal by signaling in the reference clock domain.

Abstract: Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.