Abstract: A composite address resolution scheme is used in a distributed processing computer communications system. Many parallel processors are connected together via a multi-processor intertie bus, which serves to communicate data from any processor to any other processor. Resolution of control among several competing processors which desire access to the bus is resolved directly on the bus. The processors are online replaceable; and the system fails soft. Each processor contains resolution logic which enables simultaneous parallel resolution by any number of processors. The resolution is performed on the basis of a composite logical address (CLA) which originates within each processor. The CLA can contain non-unique priority information as well as unique logical location information. The bus is awarded to the processor exhibiting the lowest CLA. The resolution is performed starting with the most significant bit or bits and working downward towards the least significant bit or bits.

Abstract: A fully distributed computing system comprises several processors, each having an arbitrarily long unique logical address. A bidirectional bus connects each of the processors and is used for communicating information between and among processors, and for resolving requests from a competing set of processors desiring access to the bus for subsequent communication with another processor. Resolving apparatus, comprising pan-processor control lines and a resolution member within each processor, awards bus access to that competing processor having the lowest logical address. All control lines within the resolving apparatus are bidirectional; as a result, the system "fails soft," i.e., there is no single point of failure in the system; one of the processors can fail without disrupting the operation of the remainder of the system. Each processor's resolution member comprises one or more resolve elements, which can be single-bit, dual-bit, or multi-bit resolve elements.