Abstract: A reconfigurable applicator system for extrusive dispensing of a work material is provided. The system includes a body portion having an actuator coupled thereto. A frame portion coupled to the body portion defines a support structure for at least one cartridge unit containing the work material. A combination trigger handle portion is coupled to the body portion to be adjustable between angularly displaced first and second grip positions relative to the frame portion. The combination trigger handle portion includes at least first and second selectable triggers coupled to the actuator, which responds to each of the first and second triggers to actuate extrusive dispensing of the work material from the cartridge unit. The combination trigger handle portion in the first and second grip positions alternatively configures the system between overhand and underhand configurations.

Abstract: An integrated circuit structure is provided with an inductor formed therein which comprises a metal coil on an insulated surface over a semiconductor substrate, and a high magnetic susceptibility cobalt/nickel metal core located adjacent said metal coil, but spaced therefrom by one or more insulation layers. In one embodiment, the high magnetic susceptibility cobalt/nickel metal core is placed between lower and upper portions of the metal coil which are interconnected together by filled vias. In another embodiment, the metal coil is formed in a serpentine shape in one plane on an insulated surface over the semiconductor substrate, and the high magnetic susceptibility cobalt/nickel metal core is formed over the serpentine coil, but spaced from the serpentine coil by another insulation layer.

Abstract: A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C<(A+D+E), the second section being spaced from the first section along said reference axis; and a third section which extends at an angle to the reference axis and joins adjacent ends of the first and second sections.

Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell includes the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

Abstract: Four electric field containment regions are formed in a semiconductor substrate by implanting ions into the substrate along four axes that are angularly oriented about a normal to a surface of the substrate in four orthogonal directions respectively. The implant axes are further angularly tilted from the normal by a large angle on the order of 45.degree. such that the axes intersect the normal at a point below the surface. A field effect transistor (FET) is formed in the substrate above the containment regions such that the FET is substantially centered about the normal and has a channel that is aligned with one of the four orthogonal directions. A source and drain are formed at opposite ends of the channel. The containment regions formed under the source and drain respectively are configured to contain electric fields extending therefrom and thereby suppress punchthrough. The four containment regions are implanted at angles that minimize channeling, and any channeling that does occur is symmetrical.

Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: An integrated circuit structure, and a method of making same is disclosed wherein one or more patternable busses of conductive material (such as polysilicon) interconnect electrode strips (such as gate electrode strips) of the same conductive material formed over active areas (such as MOS islands). The busses are formed on the structure over field oxide portions thereon during the initial step of patterning the layer of conductive material to expose the active areas and to form the electrodes thereover. After further processing to form other electrode regions in the active areas (e.g., source and drain regions in N-MOS and P-MOS islands), but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections, as desired, between various electrodes in the integrated circuit structure.