Abstract: An error correction code (ECC) block for a data storage disk, includes an array of data that is 88 rows by 172 columns. Each row includes ten bytes of inner parity code and each column includes sixteen bytes of outer parity making the array 104 rows by 182 columns. The ECC block is divided into eight sectors, each sector having eleven rows of data and two associated rows of outer parity, for a total of thirteen rows per sector. The ECC block in accordance with the present invention is half the size of a conventional ECC block but has a higher ratio of parity bytes to data. Consequently, the ECC block of the present invention is particularly advantageous with small form factor disks and first-surface media, i.e., disks with the recording layer on the exterior of the disk or under a very thin transparent layer.

Abstract: A data storage disk includes a writeable area that allows a user to write data, wherein the data files are written from the outside diameter towards the inside diameter of the writeable area, while file system information is written from the inside diameter towards the outside diameter of the writeable area. This optimizes the use of the writeable area, whether a large number of small data files or a small number of large data files are being stored. To further optimize the use of the writeable area, information may be stored in two or more different error correction code (ECC) block sizes. Thus, information, such as the file system attributes and linking sectors, which contains few bytes may be stored in the smaller ECC block size, while the data may be stored in the larger ECC block size. The data storage disk, may also include a mastered content area.

Abstract: A disc drive includes a base and a disc rotatably attached to the base. A controller for a disc drive uses a system for mapping logical block addresses to actual location on a disc drive stores the number of skipped or defective sectors which occur prior to a target cylinder in a cylinder skip table. The system estimates a starting cylinder location for the selected logical block address. After estimating the cylinder location, a number of skipped defective sectors that have occurred prior to a cylinder start is determined. The starting location of the cylinder is slipped by this amount. A target track and associated head is also determined. Information in the track identification field is used to adjust the actual location on the track and to determine if a track seek to another track is needed.

Abstract: A method and system for managing a plurality of defects that may cause an error during a write operation in a write-once data storage disk is provided. A host system sends a write command to a disk drive that contains the storage disk. The process detects any errors that may occur during the write operation. When an error is detected, a “skip list” containing the addresses of physical sectors on the disk that are to be skipped during a read operation is updated, the write operation is suspended, and the process attempts to rewrite the data in another sector. If the rewrite is performed successfully, the write operation continues. Otherwise, the write operation is terminated and the host device is notified. While the disk drive is operative, the skip list is preferably maintained in a buffer memory, but periodically the entries in the skip list are copied to the disk for permanent storage. Before a read operation begins, the skip list is copied from the disk to the memory.

Abstract: An error correction code (ECC) block for a data storage disk, includes an array of data that is 88 rows by 172 columns. Each row includes ten bytes of inner parity code and each column includes sixteen bytes of outer parity making the array 104 rows by 182 columns. The ECC block is divided into eight sectors, each sector having eleven rows of data and two associated rows of outer parity, for a total of thirteen rows per sector. The ECC block in accordance with the present invention is half the size of a conventional ECC block but has a higher ratio of parity bytes to data. Consequently, the ECC block of the present invention is particularly advantageous with small form factor disks and first-surface media, i.e., disks with the recording layer on the exterior of the disk or under a very thin transparent layer.

Abstract: A single chip integrated disc/servo controller and processor (CPU) for a disc drive reduces timing overhead associated with processor/controller/memory communication paths, increases speed, reduces the number of ASIC components, and increases reliability. The processor has a core that can be customized and implemented with appropriate hard disc drive specific controller technology including code or algorithms. Timing overhead associated with the conventional multi-chip communication paths is reduced by the inventive structure as the single on-chip processor has direct access to a buffer memory through a buffer manager within the controller logic. This eliminates the pin and pad delays that are present in conventional implementations. This performance increase has a direct positive impact on disc drive performance generally, and more particularly on disc drive performance when running code from the buffer memory.

Abstract: A data sector/servo split generator is disclosed for a disk drive apparatus implementing a zone bit recording format and having an embedded sector servo system where servo sector fields split at least one data field on a surface of a disk in the disk drive apparatus. A first counter is provided to count an amount of time to the beginning of a data field, and a first signal (SECTOR) is generated to indicate when the beginning of a data field is encountered by a read/write head in the disk drive. A second signal (SPLIT.sub.-- VALID) is generated by the data sector/servo split generator if a next data field after the generation of the SECTOR signal is split by a servo sector field. A second counter counts a predetermined number of data bytes transferred between a surface of a disk in said disk drive apparatus and said disk controller, so that a third signal (SPLIT) is generated, the SPLIT.sub.-- VALID signal is generated, when a servo sector is encountered in a data field by the read/write head.

Abstract: A controller in a hard disk drive system for controlling the transfer of data and control signals between a plurality of host processors and the disk drive system. The disk drive system including storage media, at least one transducer for recording data on and retrieving data from the storage media and an actuator for moving the transducers with respect to the storage media. The controller includes a programmed first microprocessor operating under control of a first operating system stored in a first memory unit associated with the first microprocessor for controlling the recording of data on and the retrieval of data from the storage media, the controlling of the actuator to locate the transducer at and to maintain the transducer at a specified location with respect to the storage media.

Abstract: A multi-layer data integrity system for use in a disk drive controller for ensuring the data integrity as data is transferred through the controller and written and fetched from the disk media. The disk drive controller is partitioned into an interface controller and a low level controller where the interface controller controls the transfer of data to and from the host processor and the low level controller controls the recording and reading from the disk media. The interface controller employs a first error encoding and detecting means for encoding the data as originally received from the host processor. The low level controller employs an error encoding and detecting means for encoding both the received data and the encoding data which was appended to the data received by the interface controller. The low level controller's error encoding and detecting means corrects errors detected in recovered data.

Abstract: A high level controller for maintaining communication with a host processor via a host processor interface for establishing communication paths between the host processor interface, an internal processor and a plurality of storage means. A first means receives indicia from the internal processor where the indicia specifies one of the communication paths and generates control signals for forming the specific communication path requested. A second means receives the control signals from the first means and forms the requested communication path. A third means is connected to the first and second means for controlling the communication of the system with the host processor interface in accordance with control signals generated by the first means. In this manner various data paths for communication between the host interface, internal processor and a plurality of storage means may be adaptably specified and formed to make optimum use of the system.

Abstract: A disk drive architecture controls the transfer of data between a host processor interface and a recording media that includes one or more disk surfaces for storing data. A low-level data controller controls the transfer of data between the disk surfaces and a data buffer. An interface controller controls the transfer of data between the host interface and the data buffer. An arbiter and buffer controller, responsive to data transfer requests from the low-level and interface controllers, arbitrates data storage and retrieval accesses of the data buffer. The low-level and interface controllers operate substantially independent of one another in performing their respective control operations. Consequently, data is transferred bi-directionally through the data buffer at the optimum timing for both controllers.