Patents by Inventor Stanton MacDonough Keeler
Stanton MacDonough Keeler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9977732Abstract: The disclosure is related to systems and methods of nonvolatile data caching. In some embodiments, circuits or methods may be configured to store selected data to a nonvolatile data cache based on selection criteria. The selection criteria may be based on previous data access commands. The selection criteria may relate an amount of resources, such as time or power, needed to retrieve the selected data from a data storage medium. The selected data may be retrieved from the data storage medium and stored at the nonvolatile data cache during an idle state.Type: GrantFiled: March 31, 2011Date of Patent: May 22, 2018Assignee: Seagate Technology LLCInventors: Stanton MacDonough Keeler, Steven Scott Williams, Robert William Dixon
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Patent number: 9348747Abstract: Systems and methods are disclosed for improving performance in of storage device latency. In an embodiment, an apparatus may comprise a controller configured to receive a first data access command at a device including a nonvolatile solid state memory and a disc memory, and when the first data access command is directed to the nonvolatile solid state memory, store the first data access command to a first command queue for the nonvolatile solid state memory. In another embodiment, a method may comprise receiving, at a data storage device, a first data access command, storing the first data access command in a first command queue, determining whether the data access command is directed to a Flash memory or a disc memory, and storing the first data access command in a second command queue when the first data access command is directed to the Flash memory.Type: GrantFiled: October 29, 2013Date of Patent: May 24, 2016Assignee: Seagate Technology LLCInventors: Stanton MacDonough Keeler, Margot Ann LaPanse
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Publication number: 20160011966Abstract: Systems and methods are disclosed for improving performance in of storage device latency. In an embodiment, an apparatus may comprise a controller configured to receive a first data access command at a device including a nonvolatile solid state memory and a disc memory, and when the first data access command is directed to the nonvolatile solid state memory, store the first data access command to a first command queue for the nonvolatile solid state memory. In another embodiment, a method may comprise receiving, at a data storage device, a first data access command, storing the first data access command in a first command queue, determining whether the data access command is directed to a Flash memory or a disc memory, and storing the first data access command in a second command queue when the first data access command is directed to the Flash memory.Type: ApplicationFiled: October 29, 2013Publication date: January 14, 2016Applicant: Seagate Technology LLCInventors: Stanton MacDonough Keeler, Margot Ann LaPanse
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Patent number: 9213646Abstract: Systems and methods are disclosed for cache data value tracking. In an embodiment, a controller may be configured to select data; set a node weight for the data representing a cache hit potential for the data; store a first time stamp value for the data representing when the data was accessed; and store the data in a cache memory based on the node weight and the first time stamp value. In another embodiment, a method may comprise setting a node weight for data associated with a data access command, storing a first access counter value for the data representing a number of times new data has been stored to the cache memory when the data was accessed, and removing the data from the cache memory or maintaining the data in the cache memory based on the node weight and the first access counter value.Type: GrantFiled: June 20, 2013Date of Patent: December 15, 2015Assignee: Seagate Technology LLCInventors: Margot Ann LaPanse, Joseph Masaki Baum, Stanton MacDonough Keeler, Michael Edward Baum, Thomas Dale Hosman, Robert Dale Murphy
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Patent number: 9201790Abstract: The present disclosure is directed to systems and methods of matching data rates. In a particular embodiment, a device includes a first data bus and a controller having a first output coupled to the first data bus to provide data to the first data bus. The device also includes a first memory of a first type coupled to the first data bus. The first memory may have a first input to receive data from the controller via the first data bus. The device also includes logic coupled to the first data bus. The logic may have a second input coupled to the first data bus to receive data from the controller via the first data bus. The device may also include a second data bus coupled to the logic. The logic may have a second output coupled to the second data bus to provide data to the second data bus. The logic may also include a second memory of a second type coupled to the second data bus. The second memory may have a third input to selectively receive data from the logic via the second data bus.Type: GrantFiled: October 9, 2007Date of Patent: December 1, 2015Assignee: Seagate Technology LLCInventors: Stanton MacDonough Keeler, Todd Strope
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Patent number: 9189332Abstract: A circuit may be configured to increase the data retention reliability of non-volatile solid state memory (NVSSM) by writing a parity block, which can contain user data pages and parity data pages. A circuit can also be configured to store the parity data pages based on whether the user data pages in the block have been filled, on elapsed time, or during a power down event.Type: GrantFiled: September 13, 2013Date of Patent: November 17, 2015Assignee: Seagate Technology LLCInventors: John Edward Moon, Stanton MacDonough Keeler
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Patent number: 8583986Abstract: In a particular embodiment, a storage device is disclosed that includes a solid-state storage media. The storage device further includes a read/write circuit including an error correction coding (ECC) encoder/decoder adapted to write data and associated ECC information to the solid-state storage media without performing a read-verify operation.Type: GrantFiled: December 17, 2008Date of Patent: November 12, 2013Assignee: Seagate Technology LLCInventors: Stanton MacDonough Keeler, John Edward Moon
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Publication number: 20100153821Abstract: In a particular embodiment, a storage device is disclosed that includes a solid-state storage media. The storage device further includes a read/write circuit including an error correction coding (ECC) encoder/decoder adapted to write data and associated ECC information to the solid-state storage media without performing a read-verify operation.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: Seagate Technology LLCInventors: Stanton MacDonough Keeler, John Edward Moon
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Publication number: 20100153635Abstract: In a particular embodiment, a circuit device is disclosed that includes a first interface to a high speed data bus of a host system and a second interface coupled to a first data storage device. The circuit device further includes a solid-state storage device having a first solid-state data storage medium and having at least one expansion slot to receive at least one second solid-state data storage medium to expand a memory capacity of the solid-state storage device. The circuit device also includes a control circuit adapted to receive data from the host system via the first interface and to selectively write the received data to one of the first data storage device and the solid-state storage device.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: Seagate Technology LLCInventors: Margot Ann LaPanse, Michael Edward Baum, Stanton MacDonough Keeler
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Publication number: 20090094389Abstract: The present disclosure is directed to systems and methods of matching data rates. In a particular embodiment, a device includes a first data bus and a controller having a first output coupled to the first data bus to provide data to the first data bus. The device also includes a first memory of a first type coupled to the first data bus. The first memory may have a first input to receive data from the controller via the first data bus. The device also includes logic coupled to the first data bus. The logic may have a second input coupled to the first data bus to receive data from the controller via the first data bus. The device may also include a second data bus coupled to the logic. The logic may have a second output coupled to the second data bus to provide data to the second data bus. The logic may also include a second memory of a second type coupled to the second data bus. The second memory may have a third input to selectively receive data from the logic via the second data bus.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Applicant: SEAGATE TECHNOLOGY, LLCInventors: Stanton MacDonough Keeler, Todd Strope