Abstract: The present disclosure relates to a processing arrangement for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement for determining a digital output value from a digital input value based on a linear function and a square root function. The processing arrangement includes a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function. A selector is configured to select, based on a comparison between the digital input value and a threshold value, whether the digital output value is determined by the first calculation block or by the second calculation block.

Abstract: A calculation processor for determining a digital output value from a digital input value based on an exponent value a, the processor comprising a first calculation block, a second calculation block and a final calculation block. The first calculation block initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value.

Abstract: A calculation processor for determining a digital output value (OUT) from a digital input value (IN) based on an exponent value a, the processor comprising a first calculation block (CB1), a second calculation block (CB2) and a final calculation block (CBF). The first calculation block (CB1) initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value.

Abstract: The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system.

Abstract: A Digital Subscriber Line [DSL] or Very High Speed Digital Subscriber Line [VDSL] telecommunication device with a downstream path and an upstream path, each path comprising a plurality of processors interconnected with a plurality of memories. The processors and the memories are arranged as input/output border column and row of an interconnecting matrix architecture constituted by interconnection devices able to interconnect the processors of the column with the memories of the row. This arrangement allows mapping different architectures simply by changing the status of the interconnection devices. The matrix arrangement provides a very flexible simulation platform for different possible applications and, even when implemented on silicon, the ASIC has a maximum of flexibility and can be adapted to different standard.

Abstract: A Digital Subscriber Line [DSL] telecommunication device comprising at least one common memory (CM) that is shared between circuits (FFT, Demapper) of the downstream path and corresponding circuits (Mapper, IFFT) of the upstream path. The shared or common memory (CM) advantageously replaces the known two distinct memories (DM, UM) generally used, one for the downstream path and the other for the upstream path. The single common memory (CM) is particularly adapted to Very High Speed Digital Subscriber Line [VDSL−, VDSL or VDSL+] devices where the two downstream frequency ranges (DF1, DF2) are separated by an upstream frequency range (UF1); and a where a second upstream frequency range (UF2) may exist. The size of the common memory shared by the fourth circuits is slightly larger (2800 carriers of 16 bits) than one (2048 carriers of 16 bits) of the known two memories interfacing each only two circuits of a same path.

Abstract: An integrated modem circuits comprising processor-systems (1) and hardware (2,3) for exchanging signals with another modem circuit 1 Mb/s or more are provided with low cost, accurate, flexible filter software (11) for embodying a digital phase locked loop filter. Said hardware (2,3) comprises fast modules (22,32) for compensating for sample processing. The insight of hardware phase locked loops being expensive, not accurate, inflexible and of software phase locked loops being slow results in the basic idea of the phase locked loop calculations being done in software and the compensations being done in hardware. Sample software (14,15) processes samples (shifting-adding-deleting). Said hardware (2,3) comprises in the transmission path (2) mappers (21), rotors (22) and inverse Fourier transformators (23) and in the receiving path (3) Fourier transformators (33), rotors (32) and demappers (31). Control software (12,13) controls said rotors (22,32).

Abstract: The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system.

Abstract: An interfacing device (INT) which extracts M outgoing sets of bits (OS1, OS2, . . . , OSM) out of N incoming sets of bits (IS1, IS2, . . . , ISN), M being smaller than N, includes: a. an incoming register (IR) wherein the N incoming sets of bits (IS1, IS2, . . . , ISN) are temporarily stored; and b. a selector (SEL) comprising a multiplexer bank (MUX) with M multiplexers (MUX1, MUX2, . . . , MUXM) each having N−M+1 inputs and one output, and a control unit (CTRL) for the multiplexer bank (MUX). The distinct sets of N−M+1 incoming sets of bits that are applied to distinct multiplexers overlap and the control unit (CTRL) can control the multiplexers (MUX1, MUX2, . . . , MUXM) so that an appropriate order is respected by the outgoing sets of bits (OS1, OS2, . . . , OSM).

Abstract: An interfacing device (INT) which replaces M outgoing sets of bits out of N outgoing sets of bits (OS1, OS2, . . . , OSN) by M incoming sets of bits (IS1, IS2, . . . , ISM), M being smaller than N, includes:a. an outgoing register (OR) wherein the N outgoing sets of bits (OS1, OS2, . . . , OSN) are temporarily stored; andb. a selection means (SEL) comprising a multiplexer bank (MUX) with N multiplexers (MUX1, MUX2, . . . , MUXN) each having one output and at most M inputs whereto at most M incoming sets of bits are applied, and a control unit (CTRL) for the multiplexer bank (MUX). The control unit (CTRL) can control the multiplexers (MUX1, MUX2, . . . , MUXN) so that an appropriate order is respected by the outgoing sets of bits (OS1, OS2, . . . , OSN).