Abstract: A system can include a microprocessor having a prefetch queue including a plurality of slots configured to store program counter values (PCVs) and instructions, a pipeline configured to receive instructions from the prefetch queue, and a select circuit coupled to the prefetch queue. The select circuit may selectively freeze a first slot of the plurality of slots and selectively output a frozen PCV and a frozen instruction from the first slot while frozen. The microprocessor can include write logic coupled to the prefetch queue and a comparator circuit coupled to the prefetch queue and the select circuit. The write logic may load data into unfrozen slots of the prefetch queue. The comparator circuit may compare a target PCV with the frozen PCV to determine a match. The select circuit indicates, to the pipeline, whether the frozen instruction is valid based on the comparing.

Abstract: A dual-port block random access memory (BRAM) can include first and second sections including direct mapped cache entries. The dual-port BRAM further can include third and fourth sections including translation look-aside buffer entries, wherein entries of the third section are associated with entries of the fourth section and wherein an entry of the third section and an associated entry of the fourth section collectively specify complete translation look-aside buffer data. The dual-port BRAM also can include first and second address ports concurrently accessing at least one of the first, second, third, or fourth sections of the dual-port BRAM to locate a virtual address to be translated.