Abstract: The invention relates to semiconductor devices comprising logic, or low-noise, transistors, or transistors for very high frequencies whose structure is improved with respect to the dimensions, the series resistance value, and/or the gain. Such semiconductor devices may be integrated into a semiconductor body having surfaces with contact windows covered with layers of metal combined with the material of the semiconductor body. A multi-collector transistor structure is also formed.

Abstract: A slave-type interface circuit which can receive signals from a bus if the coding A.sub.0, A.sub.1 and A.sub.2 of its inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to that mode of operation. The signals from the bus are then delivered to the inputs L.sub.1 and L.sub.2. With another mode of operation the coding of inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to off-line operation on the basis of logic levels applied to the same inputs L.sub.1 and L.sub.2. A branching block (SBL) directs the signals from the inputs L.sub.1 and L.sub.2 either to a bus receiver RBUS or directly to a decoder CDEC controlling a group of switches (COM). In the case of operation with a bus, the bus receiver (RBUS) controls the logic for the progress for operations.

Abstract: A high-frequency differential-amplifier stage. The collectors of the transistors (T.sub.1, T.sub.2) are connected to the emitters of two transistors (T.sub.3, T.sub.4) coupled to provide feedback between their collectors and their bases and which are biased by means of resistors (R.sub.1, R.sub.2). This input stage forms a resonant circuit. Two current sources (R.sub.32, T.sub.32, R.sub.31, T.sub.31) improve the operation of this stage in the saturated mode.

Abstract: In the method according to the invention conductive electrodes are provided with the aid of a mask aligned with respect to at least two contact windows present in an insulating layer. First, layers of metal combining with semiconductor material, for example, Pt silicide, are provided in the contact windows. A narrow region of the insulating layer between the two contact windows may have a reduced dimension because in their extreme relative positions the conductive electrodes can only partially cover the contact windows. The invention also relates to semiconductor devices comprising logic (or low-noise) transistors, or transistors for very high frequencies whose structure is improved with respect to their dimensions, their series resistance value and/or their gain.

Abstract: The invention relates to a high-frequency amplifier which comprises only two cascaded differential stages. The collectors of the transistors (T.sub.1, T.sub.2) of the differential input stage are connected to the emitters of two transistors (T.sub.3, T.sub.4) which have feedback between their collectors and bases and which are biased by means of resistors (R.sub.1, R.sub.2). This input stage forms a resonant circuit. The differential output stage comprises transistors (T.sub.6 and T.sub.7) whose emitters are interconnected by a phase-lead capacitor (C.sub.1) and two resistors (R.sub.8, R.sub.9). Such an arrangement enables a high gain to be obtained over the entire operating frequency range of the amplifier and in particular for high frequencies.

Abstract: A slave-type interface circuit operating with a series bus in a configuration in which writing takes place after recognition of an address. A cycle transmitted by the bus contains an address sequence and a data sequence.The circuit controls a plurality of user circuits (COM) on the basis of data stored in a memory (M) and of a decoder (CDEC).A register (REG) and a bus logic (BUSL) receive at their inputs (L.sub.1, L.sub.2) information (SDA) and clock (SCL) signals. The bus logic (BUSL) receives from an identification circuit (AIC) a signal (DVA) indicating whether or not the address transmitted by the bus corresponds to an address A.sub.0, A.sub.1, A.sub.2 displayed at the inputs S.sub.0, S.sub.1 and S.sub.2. It controls the circuit on the basis of the register (REG) initialization signal (RST1), a signal LDS) for the authorization of the loading of data into the memory (M) and an acceptance signal (ACK) transmitted in the direction of the bus.