Abstract: There is shown and described, inter alia, a holder for supporting a headrest, which holder can be fixed in a retaining structure of a vehicle by insertion in a first mounting direction, wherein the holder is formed with a guide passage for receiving a retaining rod of the headrest, and wherein the holder has fixing means for fixing to a retaining structure of the vehicle.

Abstract: A guide device for a retaining rod of a headrest, having a guide structure forming a channel for guiding and supporting the retaining rod, having a latch device including a latch movable between a latching position and a release position. The latch cooperates with a latch structure of the retaining rod to prevent movement of the retaining rod relative to the guide structure in at least one direction. In the latching position the latch device is engaged with the latch structure of the retaining rod and in the release position the latch is disengaged from the latch structure. The latch device has a locking device movable between a locking position and a disengagement position and has a locking structure which, in the locking position, is in the movement path of the latch to prevent movement from the latching position into the release position and, in a disengagement position, enable movement of the latch into a release position.

Abstract: There is shown and described, inter alia, a holder for supporting a headrest, which holder can be fixed in a retaining structure of a vehicle by insertion in a first mounting direction, wherein the holder is formed with a guide passage for receiving a retaining rod of the headrest, and wherein the holder has fixing means for fixing to a retaining structure of the vehicle.

Abstract: A guide device for a retaining rod of a headrest, having a guide structure forming a channel for guiding and supporting the retaining rod, having a latch device including a latch movable between a latching position and a release position. The latch cooperates with a latch structure of the retaining rod to prevent movement of the retaining rod relative to the guide structure in at least one direction. In the latching position the latch device is engaged with the latch structure of the retaining rod and in the release position the latch is disengaged from the latch structure. The latch device has a locking device movable between a locking position and a disengagement position and has a locking structure which, in the locking position, is in the movement path of the latch to prevent movement from the latching position into the release position and, in a disengagement position, enable movement of the latch into a release position.

Abstract: A method and a device for checking a circuit path of a circuit for adherence to set-up and hold times are provided. A timing behavior of the circuit path is designated as being correct if at least one pair of set-up and hold times from predefined set-up and hold times that are for the circuit path does not produce any timing infringement in the circuit path. Otherwise, the timing behavior of the circuit path is classified as being defective. This decreases the number of circuit paths wrongly designated as being defective by the use of pairs of predefined set-up and hold times and decreases the chip area for buffers.

Abstract: Various aspects of this disclosure provide a circuit arrangement, including: an input; a first latch circuit coupled to the input, the first latch circuit including a first forward inverter and a first feedback inverter; a switch, wherein a first terminal of the switch is coupled to an output of the first forward inverter; a second latch circuit coupled to a second terminal of the switch; an output coupled to the second latch circuit; and an isolating circuit configured to isolate the first forward inverter from an input of the first feedback inverter.

Abstract: Methods and apparatuses for performing timing analyses of an electronic circuit are provided. Waveforms of signals in the circuit are determined, and timing checks are performed based on these waveforms.

Abstract: A method for estimating a terminal capacitance associated with a terminal of a cell of a digital circuit includes providing first and second capacitance values associated with an upper and lower bound, respectively, on the terminal capacitance, providing results of a timing analysis of the digital circuit, and determining an estimation value for the terminal capacitance based on the results of the timing analysis and at least one of the first and second capacitance values. A system for estimating a terminal capacitance includes a storage unit which stores the first and second capacitance values and a processor which performs a timing analysis of the digital circuit and determines an estimation value for the terminal capacitance based on the timing analysis and at least one of the first and second capacitance values.

Abstract: Methods and apparatuses for performing timing analyses of an electronic circuit are provided. Waveforms of signals in the circuit are determined, and timing checks are performed based on these waveforms.

Abstract: A method for estimating a terminal capacitance associated with a terminal of a cell including a digital circuit includes providing first and second capacitance values associated with an upper and lower bound, respectively, on the terminal capacitance, providing results of a timing analysis of the digital circuit, and determining an estimation value for the terminal capacitance based on the results of the timing analysis and at least one of the first and second capacitance values. A system for estimating a terminal capacitance includes a storage unit which stores the first and second capacitance values and a processor which performs a timing analysis of the digital circuit and determines an estimation value for the terminal capacitance based on the timing analysis and at least one of the first and second capacitance values.

Abstract: According to the invention a characteristic property of an electronic circuit component depending on at least one variable (X1, X2) is approximated by an approximating function. This is accomplished by dividing a total range of said least one variable into a number of sub-ranges by inserting dividing nodes (4), and approximating characterization data points (2) in each of the sub-ranges by an elementary function, wherein the elementary functions defined in the sub-ranges join together to form said approximating function defined in said total range. The approximation is accomplished such that the approximating function is continuously partial differentiable with respect to said at least one variable (X1, X2) in the dividing nodes (4).

Abstract: A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

Abstract: A method and a device for checking a circuit path of a circuit for adherence to set-up and hold times are provided. A timing behavior of the circuit path is designated as being correct if at least one pair of set-up and hold times from predefined set-up and hold times that are for the circuit path does not produce any timing infringement in the circuit path. Otherwise, the timing behavior of the circuit path is classified as being defective. This decreases the number of circuit paths wrongly designated as being defective by the use of pairs of predefined set-up and hold times and decreases the chip area for buffers.

Abstract: A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

Abstract: According to the invention a characteristic property of an electronic circuit component depending on at least one variable (X1, X2) is approximated by an approximating function. This is accomplished by dividing a total range of said least one variable into a number of sub-ranges by inserting dividing nodes (4), and approximating characterization data points (2) in each of the sub-ranges by an elementary function, wherein the elementary functions defined in the sub-ranges join together to form said approximating function defined in said total range. The approximation is accomplished such that the approximating function is continuously partial differentiable with respect to said at least one variable (X1, X2) in the dividing nodes (4).