Patents by Inventor Stefan BERGLUND

Stefan BERGLUND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996474
    Abstract: The present disclosure relates to a bipolar transistor semiconductor device including: a substrate layer, a collector epitaxial layer supported by the substrate layer, a base region supported by a portion of the collector epitaxial layer, and an emitter region supported by a portion of the base region. The emitter region includes a polysilicon material.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 28, 2024
    Assignee: Nexperia B.V.
    Inventors: Stefan Berglund, Steffen Holland
  • Patent number: 11933107
    Abstract: A disc cutter for a cutting unit used in an undercutting operation and a method of producing the same. The disc cutter including an annular disc body made of a metal alloy or metal matrix composite having a first side, a second side arranged substantially opposite to the first side and a radially peripheral part. At least one metal alloy, metal matrix composite or cemented carbide cutting part is mounted in and substantially encircling the radially peripheral part of the disc body which protrudes outwardly therefrom to engage with the rock during the mining operation. The at least one cutting part is made from a material having a higher wear resistance than the material used for the disc body, wherein the disc body and the cutting part are joined by diffusion bonds.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 19, 2024
    Assignee: Sandvik Mining and Construction Tools AB
    Inventors: Bjorn Claesson, Stefan Ederyd, Johan Sundstrom, Tomas Berglund, Fredrik Meurling
  • Publication number: 20240072113
    Abstract: A vertical semiconductor device and method for manufacturing the same is provided. The semiconductor device includes a body with a substrate and an epitaxial layer on the substrate, the layer includes a first region of a first conductivity type, and a second region of a second different conductivity type, the second region is arranged opposite to the substrate with respect to the first region, and when viewed in a first direction from the layer to the substrate, the first region and the second region each extend across an entire area of the body. The device further includes a trench arranged in the body, extending through the second region and at least partially into the first region, thereby dividing the second region into an inner and an outer portion that are mutually electrically isolated, and a first conductive contact on the second region to enable electrically accessing the inner portion.
    Type: Application
    Filed: August 30, 2023
    Publication date: February 29, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Stefan Berglund, Tim Böttcher, Steffen Holland, Seong-Woo Bae, Detlef Oelgeschlaeger
  • Publication number: 20230307494
    Abstract: A vertical oriented semiconductor device is provided that includes a semiconductor body having a first major surface, the semiconductor body includes a first region of a first conductivity type, a second region of a second conductivity type, and the second region is adjacent the first region so that a junction is provided between the first region and the second region. The junction has a maximum distance to the first major surface, and the semiconductor device further includes a trench extending into the semiconductor body from the first major surface to an extension depth at least equal to the maximum distance. The trench includes a material arranged to provide electrical insulation to limit a lateral field termination distance associated with the junction.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 28, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Stefan Berglund, Steffen Holland, Tim Böttcher, Seong-Woo Bae
  • Publication number: 20230230892
    Abstract: A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 20, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Regnerus Hermannus Poelma, Hartmut Bünning, Stefan Berglund, Hans-Juergen Funke, Johannes Josinus Kuipers, Joep Stokkermans, Wolfgang Schnitt
  • Publication number: 20230074779
    Abstract: A method of provisioning a communication service instance to a customer. The method performed at a network slice management function, NSMF, comprises receiving from a communications service management function, CSMF, a first message requesting an operation on at least one network slice instance, NSI. The first message comprises attributes and their values defining at least one service profile. The method further comprises sending to a network slice subnet management function, NSSMF, a second message requesting an operation on at least one network slice subnet instance, NSSI. The second message comprises attributes and their values defining at least one slice profile, wherein the at least one slice profile is based on attributes and their values defining profiles of at least one customer facing service, CFS, and at least one resource facing service, RFS, associated with said at least one customer facing service, CFS.
    Type: Application
    Filed: February 5, 2021
    Publication date: March 9, 2023
    Inventors: Paul STJERNHOLM, Oscar ZEE, Stefan BERGLUND
  • Publication number: 20220020670
    Abstract: A semiconductor device is provided that includes a frontside and a backside, four sidewalls, a first solder/glue connection on the frontside and a second solder/glue connection on the backside. The semiconductor device is either connected as a chip scale package to a printed circuit board or inside a semiconductor package via one of the four sidewalls, so that the first solder/glue connection and the second solder/glue connection are visible for a visual solder/glue inspection.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Hartmut Bünning, Hans-Juergen Funke, Stefan Berglund, Justin Y.H. Tan, Vegneswary Ramalingam, Roelf Groenhuis, Joep Stokkermans, Thijs Kniknie
  • Publication number: 20220020679
    Abstract: A semiconductor device is provided that includes a substrate, a pocket within the substrate, a solderable/glueable re-distribution layer arranged in the pocket and a die. The die is arranged downwards, so that a base contact and an emitter contact of the die face the bottom of the device, and a collector contact of the die faces the top of the device. The solderable/glueable re-distribution layer includes a first and second re-distribution layer part and the first re-distribution layer part and the second re-distribution layer part are isolated from each other by an isolating material. The emitter contact is connected to the first re-distribution layer part and the base contact is connected to the second re-distribution layer part. The emitter contacts via the first re-distribution layer part, the base contacts via the second re-distribution layer part, and the collector contact are fan out to the top surface of the semiconductor device.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Hartmut Bünning, Hans-Juergen Funke, Stefan Berglund, Justin Y.H. Tan, Vegneswary Ramalingam, Roelf Groenhuis, Joep Stokkermans, Thijs Kniknie
  • Patent number: 10972074
    Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: April 6, 2021
    Assignee: Nexperia B.V.
    Inventors: Stefan Berglund, Soenke Habenicht, Michael Felix Konejung, Joachim Stange, Seong-Woo Bae
  • Patent number: 10720498
    Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Nexperia B.V.
    Inventors: Martin Roever, Soenke Habenicht, Stefan Berglund, Seong-Woo Bae
  • Publication number: 20200185513
    Abstract: The present disclosure relates to a bipolar transistor semiconductor device including: a substrate layer, a collector epitaxial layer supported by the substrate layer, a base region supported by a portion of the collector epitaxial layer, and an emitter region supported by a portion of the base region. The emitter region includes a polysilicon material.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Applicant: NEXPERIA B.V.
    Inventors: Stefan BERGLUND, Steffen HOLLAND
  • Patent number: 10586861
    Abstract: A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: March 10, 2020
    Assignee: Nexperia B.V.
    Inventors: Stefan Berglund, Soenke Habenicht, Steffen Holland, Tim Boettcher
  • Publication number: 20190165111
    Abstract: This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer arranged on the substrate to extend from the active region to the edge region; an isolation layer arranged on top of the first oxide layer; and a metal layer arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 30, 2019
    Applicant: NEXPERIA B.V.
    Inventors: Martin ROEVER, Soenke HABENICHT, Stefan BERGLUND, Seong-Woo BAE
  • Publication number: 20180145158
    Abstract: A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has comprises a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 24, 2018
    Applicant: NEXPERIA B.V.
    Inventors: Stefan Berglund, Soenke Habenicht, Steffen Holland, Tim Boettcher
  • Publication number: 20170302255
    Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 19, 2017
    Inventors: Stefan BERGLUND, Soenke HABENICHT, Michael Felix KONEJUNG, Joachim STANGE, Seong-Woo BAE
  • Patent number: 6098893
    Abstract: In a comfort controls system for multiple buildings (whether residential, commercial or industrial), a weather forecast unit sends weather forecast data over the Internet to a building management provider which handles building management services for a number of clients, each having a number of buildings and properties.At the provider's reception station, data on the external-building characteristics of all the buildings are compiled with the received data and then fed to the appropriate building management controls system.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: August 8, 2000
    Assignee: Honeywell Inc.
    Inventors: Ulf Stefan Berglund, Bjorn Henry Lundberg