Abstract: There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

Abstract: An image display system comprises a processor 10, a main memory 20 and a display panel 30, where the main memory 20 includes an uncompressed image area 24 for storing image data relating to an image and a compressed image area 26 for storing compressed image data. The processor is microcode-programmed, and executes, after changes have been made in the uncompressed image area, a special sequence of microcode words in a micro program memory 12 of the processor for compressing at least those parts of the uncompressed image area that are subject to changes. The microcode-compressed parts of the image data are then stored in the compressed image area 26 of the main memory. Compressed image data may then be fetched from the compressed image area 26 and decompressed for enabling generation of an appropriate image signal. The generated image signal can finally be applied to the display 30 for refreshing the image.

Abstract: An electronic timer system includes a counter-based time generator for continuously generating raw base time, and a translator for translating between raw base time and local precise time. The counter-based time generator is driven by an oscillator. The timer system further includes a temperature sensor placed in the proximity of the oscillator or a crystal used by the oscillator, and a look-up control table holding temperature values associated with corresponding control values representative of the configurable parameter value A. The look-up control table is generated when the timer system is synchronized with a synchronization source so that the temperature and control values are characteristic of the operation of the timer system in synchronization.

Abstract: An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time using configurable parameter values. The timer system can be used for generating local precise time by capturing a raw base time value from the counter-based time generator (10) in response to an external event such as a trigger pulse, and using the translator (20) to calculate local precise time from the raw base time value and the parameter values. The timer system can also be used for generating a precisely timed output signal using the translator (20) for translation from precise time of a desired timing event to raw base time. This novel design enables simple and cost-effective practical implementations, and may also support power effective operation of the timer system.

Abstract: There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically includes at least two processor cores (10), and a common internal microprogram control store (20) including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable elements (30) for providing time-shared access to the microprogram control store by the processor cores.

Abstract: An electronic timer system includes a counter-based time generator for continuously generating raw base time, and a translator for translating between raw base time and local precise time. The counter-based time generator is driven by an oscillator. The timer system further includes a temperature sensor placed in the proximity of the oscillator or a crystal used by the oscillator, and a look-up control table holding temperature values associated with corresponding control values representative of the configurable parameter value A. The look-up control table is generated when the timer system is synchronized with a synchronization source so that the temperature and control values are characteristic of the operation of the timer system in synchronization.

Abstract: An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time using configurable parameter values. The timer system can be used for generating local precise time by capturing a raw base time value from the counter-based time generator (10) in response to an external event such as a trigger pulse, and using the translator (20) to calculate local precise time from the raw base time value and the parameter values. The timer system can also be used for generating a precisely timed output signal using the translator (20) for translation from precise time of a desired timing event to raw base time. This novel design enables simple and cost-effective practical implementations, and may also support power effective operation of the timer system.

Abstract: An image display system comprises a processor 10, a main memory 20 and a display panel 30, where the main memory 20 includes an uncompressed image area 24 for storing image data relating to an image and a compressed image area 26 for storing compressed image data. The processor is microcode-programmed, and executes, after changes have been made in the uncompressed image area, a special sequence of microcode words in a micro program memory 12 of the processor for compressing at least those parts of the uncompressed image area that are subject to changes. The microcode-compressed parts of the image data are then stored in the compressed image area 26 of the main memory. Compressed image data may then be fetched from the compressed image area 26 and decompressed for enabling generation of an appropriate image signal. The generated image signal can finally be applied to the display 30 for refreshing the image.

Abstract: There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically comprises at least two processor cores (10), and a common internal microprogram control store (20) including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable means (30) for providing time-shared access to the microprogram control store by the processor cores.

Abstract: Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for storing microcode instructions; execution circuitry operable to execute microcode instructions from the control store; and means for loading a suite of one or more microcode-device modules defining an optional peripheral device, the optional peripheral device being implemented by microcode instructions executed by the execution circuitry in accordance with the definition provided by the microcode-device modules.

Abstract: The invention relates to a primary memory such as a dynamic random access memory, and a method and controller for controlling access to such a memory. The access control for the primary memory (60) is intimately associated with the microcode instructions of a processor (10) connected to the memory. The access control is integrated into the microcode program (22) of the processor, and each microcode instruction includes a control instruction used in controlling the operation of a memory controller (50). In the case of a DRAM, the DRAM controller (50) controls access to the DRAM (60) by executing, for each DRAM access, a sequence of DRAM control operations in response to a corresponding sequence of control instructions included in the microcode instructions of the processor.

Abstract: According to the invention there is provided a method for transforming a gray-level image, divided into pixels, into a black-and-white image, comprising the steps of: dividing the gray-level image into a number of generally square sub images which comprise more than one pixel; calculating and storing, for each sub image, at least one measurement value representing the gray-level of the sub image; calculating, for each sub image, a threshold value based on the measurement values of the sub image, and a number of sub images that are adjacent the sub image; and transforming, for each sub image, each pixel in the sub image to either a white or a black pixel depending upon whether the gray-level of the pixel exceeds the threshold value of the sub image or not. Preferably, parts of the gray-level image, the measurement value or values that is/are calculated, for each sub image, and the threshold value that is calculated, for each sub image, are temporarily stored in one or more memory buffers.

Abstract: A graphics processor includes a general graphics processor (30) for converting general graphics instructions into a sequence of primitive pixel oriented instructions, a queue memory (30) for storing the primitive pixel oriented instructions generated by the general graphics processor (30) in the order they are generated, and a primitive graphics processor (32) for reading and executing the primitive pixel oriented instructions in the queue memory (34) one after the other for generating pixels in an image buffer (18).