Abstract: There is provided a data processing system configured to perform data processing of a data flow application. The data processing system includes a control processor having access to memory. The data processing system further includes a plurality of programmable Processing Elements, PEs, organized in multiple clusters. Each cluster comprises a multitude of the programmable PEs, the functionality of each programmable Processing Element being defined by internal microcode in a microprogram memory associated with the Processing Element. The multiple clusters of programmable Processing Elements are arranged in a Network on Chip, NoC, connected to the control processor, which is provided as a central hub, i.e. a root, for the Network on Chip, and the multiple clusters of programmable Processing Elements being arranged at peripheral nodes, also being referred to as cluster nodes, of the Network on Chip.

Abstract: A system configured to rearrange and distribute data of an incoming image for processing by a number, K?4, of processing clusters. The incoming image has a number of scanlines, each scanline being arrangeable as a plurality of data units. The system is configured to logically partition the incoming image into K uniform regions corresponding to the number of processing clusters, wherein the K regions are defined by a number, R?2, of rows and a number, C?2, of columns, by i) dividing each scanline into a number, C?2, of uniform line segments, the length of a line segment being equal to the width of a region, ii) dividing each line segment into a number, W?2, of data units, each having a number, Q?2, of bytes, i.e. Q-byte data units, and iii) defining a region height of a number, H?2, of scanlines for each region.

Abstract: There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

Abstract: There is provided a data processing system comprising a control processor having access to memory, and a plurality of Processing Elements, PEs, organized in multiple processing clusters, each cluster comprising a multitude of said Processing Elements. The multiple processing clusters are arranged in a Network on Chip, NoC, connected, via a switch block, to the control processor, which is provided as a central hub, i.e. a root, for the Network on Chip, and the multiple processing clusters of Processing Elements being arranged at peripheral nodes, also being referred to as cluster nodes, of the Network on Chip. The Network on Chip is a network having multiple data channels connecting the switch block with the multiple processing clusters, with a point-to-point channel for each processing cluster.

Abstract: A Network on Chip, NoC, processing system configured to perform data processing. The NoC processing system is configured for interconnection with a control processor connectable to said NoC processing system. The NoC processing system comprises a plurality of microcode-programmable Processing Elements, PEs, organized in multiple clusters, each cluster comprising a multitude of said programmable PEs, the functionality of each microcode-programmable PE being defined by internal microcode in a microprogram memory associated with the PE. The clusters of programmable PE are arranged on a Network on Chip, NoC, the NoC having a root and a plurality of peripheral nodes, wherein the clusters of PE are arranged at peripheral nodes of the NoC, and the NoC is connectable to the control processor. Each cluster further includes a Cluster Controller, CC, and an associated Cluster Memory, CM, shared by the multitude of programmable PE within the cluster.

Abstract: There is provided a data processing system configured to perform data processing of a data flow application. The data processing system includes a control processor having access to memory. The data processing system further includes a plurality of programmable Processing Elements, PEs, organized in multiple clusters. Each cluster comprises a multitude of the programmable PEs, the functionality of each programmable Processing Element being defined by internal microcode in a microprogram memory associated with the Processing Element. The multiple clusters of programmable Processing Elements are arranged in a Network on Chip, NoC, connected to the control processor, which is provided as a central hub, i.e. a root, for the Network on Chip, and the multiple clusters of programmable Processing Elements being arranged at peripheral nodes, also being referred to as cluster nodes, of the Network on Chip.

Abstract: A system configured to rearrange and distribute data of an incoming image for processing by a number, K?4, of processing clusters. The incoming image has a number of scanlines, each scanline being arrangeable as a plurality of data units. The system is configured to logically partition the incoming image into K uniform regions corresponding to the number of processing clusters, wherein the K regions are defined by a number, R?2, of rows and a number, C?2, of columns, by i) dividing each scanline into a number, C?2, of uniform line segments, the length of a line segment being equal to the width of a region, ii) dividing each line segment into a number, W?2, of data units, each having a number, Q?2, of bytes, i.e. Q-byte data units, and iii) defining a region height of a number, H?2, of scanlines for each region.

Abstract: There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

Abstract: A Network on Chip, NoC, processing system configured to perform data processing. The NoC processing system is configured for interconnection with a control processor connectable to said NoC processing system. The NoC processing system comprises a plurality of microcode-programmable Processing Elements, PEs, organized in multiple clusters, each cluster comprising a multitude of said programmable PEs, the functionality of each microcode-programmable PE being defined by internal microcode in a microprogram memory associated with the PE. The clusters of programmable PE are arranged on a Network on Chip, NoC, the NoC having a root and a plurality of peripheral nodes, wherein the clusters of PE are arranged at peripheral nodes of the NoC, and the NoC is connectable to the control processor. Each cluster further includes a Cluster Controller, CC, and an associated Cluster Memory, CM, shared by the multitude of programmable PE within the cluster.

Abstract: There is provided a data processing system comprising a control processor having access to memory, and a plurality of Processing Elements, PEs, organized in multiple processing clusters, each cluster comprising a multitude of said Processing Elements. The multiple processing clusters are arranged in a Network on Chip, NoC, connected, via a switch block, to the control processor, which is provided as a central hub, i.e. a root, for the Network on Chip, and the multiple processing clusters of Processing Elements being arranged at peripheral nodes, also being referred to as cluster nodes, of the Network on Chip. The Network on Chip is a network having multiple data channels connecting the switch block with the multiple processing clusters, with a point-to-point channel for each processing cluster.

Abstract: There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

Abstract: An image display system comprises a processor 10, a main memory 20 and a display panel 30, where the main memory 20 includes an uncompressed image area 24 for storing image data relating to an image and a compressed image area 26 for storing compressed image data. The processor is microcode-programmed, and executes, after changes have been made in the uncompressed image area, a special sequence of microcode words in a micro program memory 12 of the processor for compressing at least those parts of the uncompressed image area that are subject to changes. The microcode-compressed parts of the image data are then stored in the compressed image area 26 of the main memory. Compressed image data may then be fetched from the compressed image area 26 and decompressed for enabling generation of an appropriate image signal. The generated image signal can finally be applied to the display 30 for refreshing the image.

Abstract: An electronic timer system includes a counter-based time generator for continuously generating raw base time, and a translator for translating between raw base time and local precise time. The counter-based time generator is driven by an oscillator. The timer system further includes a temperature sensor placed in the proximity of the oscillator or a crystal used by the oscillator, and a look-up control table holding temperature values associated with corresponding control values representative of the configurable parameter value A. The look-up control table is generated when the timer system is synchronized with a synchronization source so that the temperature and control values are characteristic of the operation of the timer system in synchronization.

Abstract: An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time using configurable parameter values. The timer system can be used for generating local precise time by capturing a raw base time value from the counter-based time generator (10) in response to an external event such as a trigger pulse, and using the translator (20) to calculate local precise time from the raw base time value and the parameter values. The timer system can also be used for generating a precisely timed output signal using the translator (20) for translation from precise time of a desired timing event to raw base time. This novel design enables simple and cost-effective practical implementations, and may also support power effective operation of the timer system.

Abstract: There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically includes at least two processor cores (10), and a common internal microprogram control store (20) including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable elements (30) for providing time-shared access to the microprogram control store by the processor cores.

Abstract: An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time using configurable parameter values. The timer system can be used for generating local precise time by capturing a raw base time value from the counter-based time generator (10) in response to an external event such as a trigger pulse, and using the translator (20) to calculate local precise time from the raw base time value and the parameter values. The timer system can also be used for generating a precisely timed output signal using the translator (20) for translation from precise time of a desired timing event to raw base time. This novel design enables simple and cost-effective practical implementations, and may also support power effective operation of the timer system.

Abstract: An image display system comprises a processor 10, a main memory 20 and a display panel 30, where the main memory 20 includes an uncompressed image area 24 for storing image data relating to an image and a compressed image area 26 for storing compressed image data. The processor is microcode-programmed, and executes, after changes have been made in the uncompressed image area, a special sequence of microcode words in a micro program memory 12 of the processor for compressing at least those parts of the uncompressed image area that are subject to changes. The microcode-compressed parts of the image data are then stored in the compressed image area 26 of the main memory. Compressed image data may then be fetched from the compressed image area 26 and decompressed for enabling generation of an appropriate image signal. The generated image signal can finally be applied to the display 30 for refreshing the image.

Abstract: There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically comprises at least two processor cores (10), and a common internal microprogram control store (20) including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable means (30) for providing time-shared access to the microprogram control store by the processor cores.

Abstract: A graphics processor includes a general graphics processor (30) for converting general graphics instructions into a sequence of primitive pixel oriented instructions, a queue memory (30) for storing the primitive pixel oriented instructions generated by the general graphics processor (30) in the order they are generated, and a primitive graphics processor (32) for reading and executing the primitive pixel oriented instructions in the queue memory (34) one after the other for generating pixels in an image buffer (18).