Abstract: A reliable and performant mechanism for communicating between independent processes, threads or parts of a computer system is described in which conditional atomic counters are used to manage a message queue. The conditional atomic counters control access to a message queue or memory space in a simple and reliable manner while minimizing the overhead of access to the mutex gate objects typically used in the implementation of message queues of the prior art. When implemented in software, a producer count and consumer count are maintained using conditional atomic store instructions with the condition on the store ensuring that one and only one producer or consumer of message records can actually post or receive validation of any specific message record. A counterpart implementation in hardware utilizes hardware mechanisms equivalent to those invoked by the software program.

Abstract: A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T1; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in the Icnt Counter to a predetermined count IcntMax and if the count in the Icnt Counter is at least IcntMax, then sampling the RTC to obtain a second time T2. T1 is then subtracted from T2 to obtain a time difference DT which is multiplied by ((1?1/DF)?1) to obtain a Degradation Delay DD period, DF being a constant having a value which is the desired submodel performance with respect to full performance. The Degradation Delay is instituted, the RTC is sampled from time to time to obtain a test third time T3. When a test T3 minus T2 is not less than DD, then T1 is set to T3. Then, the procedure is repeated for a next group of instructions.