Abstract: An automatic driver-dimming-mode detection protocol includes subjecting, via a dimming bus, a luminaire driver to a first driver control signal of test analog voltages. Forcing the luminaire driver, via the first driver control signal, into a power output response that includes: (a) a constant output power mode, or (b) at least two discernable different output power levels. Detecting a dimming mode of the luminaire driver. The step of detecting the dimming mode of the luminaire driver includes: measuring, via a power metering circuit, a power metering measurement corresponding to the power output response; and based on the power metering measurement of the luminaire driver being: (a) the constant output power mode, determining that the luminaire driver is a digital dimming mode type (e.g., DALI), or (b) the at least two discernable different output power levels, determining that the luminaire driver is an analog dimming mode type (e.g., 0-10V).

Abstract: A transceiver in a lighting system may include a digital isolation component having multiple channels and an isolation barrier. The digital isolation component may accept an outbound digital signal or an inbound digital signal. On a first channel, the outbound signal may be modulated with a high-frequency signal, and provided across the isolation barrier to the non-isolated side. On the non-isolated side, a modified outbound signal may be generated based on the modulated high-frequency signal. On a second channel, the inbound signal may be modulated with a high-frequency signal that is provided across the isolation barrier to the isolated side. On the isolated side, a modified inbound signal may be generated based on the modulated high-frequency signal. The transceiver may include a voltage level comparator configured to adjust voltage levels of the signals, or an edge transition or duty cycle balancer configured to adjust edges of the signals.

Abstract: An apparatus and method employ a pair of input terminals to receive an input voltage from a charging power source for charging a backup power supply for an emergency lighting system, the input voltage corresponding to any one of a plurality of nominal operating voltages. A voltage level detector produces, in response to the received input voltage, an input voltage level signal indicating which of the nominal operating voltages is being received. A temperature detector determines whether the temperature of the backup power supply exceeds a threshold and produces a temperature signal in response thereto. A heater includes a plurality of heating elements, and is activated to heat the backup power supply when the temperature of the backup power supply is less than the threshold. The input voltage level signal determines which of the heating elements is activated.

Abstract: An emergency lighting driver (100, 200, 400) includes: a power translation circuit (120, 220, 421/423/425) which receives input power from an emergency power source (10) and supplies output power to a load (20); and a programmable control device (140, 240) which controls the power translation circuit in response to a voltage feedback signal and a current feedback signal to cause the output power supplied to the load to have a programmed power output profile (302, 304), wherein the programmed power output profile is a function of time, temperature, the type of energy source employed for the emergency power source, the amount of remaining energy stored in the emergency power source, and/or the occupancy of an area in which the emergency lighting driver is located.

Abstract: A circuit (200, 300, 400, 600, 700, 800) interfacing a device (20, 30, 40, 60, 80) with a line-pair includes: a diode bridge (210) having polarity-independent input terminals coupled to the line-pair; a galvanic isolation device (230, 330) receiving a transmit signal and coupling the transmit signal to its output; a variable edge delay circuit (270, 370, 572, 574, 576) that delays rising/falling edges of the transmit signal more than falling/rising edges of the transmit signal; a voltage-controlled variable resistance element (260, 360, 460) connected across output terminals of the diode bridge; and a filter connected to a control terminal of the voltage-controlled variable resistance element. The filter includes decoupled charge and discharge paths to decouple the rise time of the transmit signal from the fall time of the transmit signal. The voltage-controlled variable resistance element couples the transmit signal to the line-pair via the diode bridge.

Abstract: An emergency lighting driver (100, 200, 400) includes: a power translation circuit (120, 220, 421/423/425) which receives input power from an emergency power source (10) and supplies output power to a load (20); and a programmable control device (140, 240) which controls the power translation circuit in response to a voltage feedback signal and a current feedback signal to cause the output power supplied to the load to have a programmed power output profile (302, 304), wherein the programmed power output profile is a function of time, temperature, the type of energy source employed for the emergency power source, the amount of remaining energy stored in the emergency power source, and/or the occupancy of an area in which the emergency lighting driver is located.

Abstract: A circuit (200, 300, 400, 600, 700, 800) interfacing a device (20, 30, 40, 60, 80) with a line-pair includes: a diode bridge (210) having polarity-independent input terminals coupled to the line-pair; a galvanic isolation device (230, 330) receiving a transmit signal and coupling the transmit signal to its output; a variable edge delay circuit (270, 370, 572, 574, 576) that delays rising/falling edges of the transmit signal more than falling/rising edges of the transmit signal; a voltage-controlled variable resistance element (260, 360, 460) connected across output terminals of the diode bridge; and a filter connected to a control terminal of the voltage-controlled variable resistance element. The filter includes decoupled charge and discharge paths to decouple the rise time of the transmit signal from the fall time of the transmit signal. The voltage-controlled variable resistance element couples the transmit signal to the line-pair via the diode bridge.

Abstract: An apparatus and method employ a pair of input terminals to receive an input voltage from a charging power source for charging a backup power supply for an emergency lighting system, the input voltage corresponding to any one of a plurality of nominal operating voltages. A voltage level detector produces, in response to the received input voltage, an input voltage level signal indicating which of the nominal operating voltages is being received. A temperature detector determines whether the temperature of the backup power supply exceeds a threshold and produces a temperature signal in response thereto. A heater includes a plurality of heating elements, and is activated to heat the backup power supply when the temperature of the backup power supply is less than the threshold. The input voltage level signal determines which of the heating elements is activated.

Abstract: A circuit (200, 300, 400, 600, 700, 800) interfacing a device (20, 30, 40, 60, 80) with a line-pair includes: a diode bridge (210) having polarity-independent input terminals coupled to the line-pair; a galvanic isolation device (230, 330) receiving a transmit signal and coupling the transmit signal to its output; a variable edge delay circuit (270, 370, 572, 574, 576) that delays rising/falling edges of the transmit signal more than falling/rising edges of the transmit signal; a voltage-controlled variable resistance element (260, 360, 460) connected across output terminals of the diode bridge; and a filter connected to a control terminal of the voltage-controlled variable resistance element. The filter includes decoupled charge and discharge paths to decouple the rise time of the transmit signal from the fall time of the transmit signal. The voltage-controlled variable resistance element couples the transmit signal to the line-pair via the diode bridge.

Abstract: A circuit (200) includes: a diode bridge (210) having polarity-independent input terminals for coupling to a DALI bus, and having positive and negative output terminals, wherein the diode bridge receives a receive signal from the DALI bus; a galvanic isolation device (220) having an input for receiving the receive signal from the diode bridge, and an output for outputting the receive signal galvanically isolated from the diode bridge and the DALI bus; a receive signal threshold reference device (235) for setting a threshold voltage for the galvanic isolation device to respond to the receive signal; an amplifier (280) for receiving the galvanically isolated receive signal from the galvanic isolation device and outputting a binary digital signal via a low pass filter (290); and a first duty cycle control device (230, 270) for adjusting the timing of rising edges of the galvanically isolated receive signal with respect to its falling edges.

Abstract: A circuit (200) includes: a diode bridge (210) having polarity-independent input terminals for coupling to a DALI bus, and having positive and negative output terminals, wherein the diode bridge receives a receive signal from the DALI bus; a galvanic isolation device (220) having an input for receiving the receive signal from the diode bridge, and an output for outputting the receive signal galvanically isolated from the diode bridge and the DALI bus; a receive signal threshold reference device (235) for setting a threshold voltage for the galvanic isolation device to respond to the receive signal; an amplifier (280) for receiving the galvanically isolated receive signal from the galvanic isolation device and outputting a binary digital signal via a low pass filter (290); and a first duty cycle control device (230, 270) for adjusting the timing of rising edges of the galvanically isolated receive signal with respect to its falling edges.

Abstract: An interface circuit interfaces a device with a line-pair. The interface circuit includes: a diode bridge having polarity-independent input terminals coupled to the line-pair, and first and second output terminals having a positive polarity and a negative polarity, respectively; a first galvanic isolation device for outputting a receive signal received on the line-pair via the diode bridge; a second galvanic isolation device receiving a transmit signal; a voltage-controlled variable resistance element connected across the positive and negative output terminals of the diode bridge; and first and second filters cascaded between the second galvanic isolation device and the voltage-controlled variable resistance element. The first filter has decoupled charge and discharge paths so as to decouple the rise time and the fall time of the transmit signal. The second filter has a voltage-dependent frequency characteristic.

Abstract: A circuit (200, 300, 400, 600, 700, 800) interfacing a device (20, 30, 40, 60, 80) with a line-pair includes: a diode bridge (210) having polarity-independent input terminals coupled to the line-pair; a galvanic isolation device (230, 330) receiving a transmit signal and coupling the transmit signal to its output; a variable edge delay circuit (270, 370, 572, 574, 576) that delays rising/falling edges of the transmit signal more than falling/rising edges of the transmit signal; a voltage-controlled variable resistance element (260, 360, 460) connected across output terminals of the diode bridge; and a filter connected to a control terminal of the voltage-controlled variable resistance element. The filter includes decoupled charge and discharge paths to decouple the rise time of the transmit signal from the fall time of the transmit signal. The voltage-controlled variable resistance element couples the transmit signal to the line-pair via the diode bridge.

Abstract: An interface circuit interfaces a device with a line-pair. The interface circuit includes: a diode bridge having polarity-independent input terminals coupled to the line-pair, and first and second output terminals having a positive polarity and a negative polarity, respectively; a first galvanic isolation device for outputting a receive signal received on the line-pair via the diode bridge; a second galvanic isolation device receiving a transmit signal; a voltage-controlled variable resistance element connected across the positive and negative output terminals of the diode bridge; and first and second filters cascaded between the second galvanic isolation device and the voltage-controlled variable resistance element. The first filter has decoupled charge and discharge paths so as to decouple the rise time and the fall time of the transmit signal. The second filter has a voltage-dependent frequency characteristic.

Abstract: A multi-port arbitration system has a write detection circuit coupled to each of a number of ports. An address coincidence detector is coupled to each of the ports. A deactivation pulse generator circuit is coupled to the address coincidence detector.

Abstract: An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register and output from a selector circuit, such as a multiplexer, when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter, the external address, or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.

Abstract: A pulsed arbitration without coincidence detection system has a pulsed arbitration circuit that is controlled by an internal write pulse and a block/group row access and that has an output coupled to a sub-word line. A sub-word line area contains the pulsed arbitration circuit.

Abstract: A synchronous memory with a shadow-cycle counter has a counter logic combiner with an address input, a registered processed-address input, an incremented-processed-address input, and a counter control input with an output that contains a processed address. A mask, counter, and mirror registers receives the processed address and has a clock input strobing around a middle of a pre-array clock cycle. An output of the mask, counter, and mirror registers forms a registered internal processed address. A clock phase shifter has a clock input and has an output coupled to the mask, counter, and mirror registers. A plane internal processed-address is coupled to the read/write control logic. An address output enable generated in the counter logic combiner is coupled to the data output enable logic.

Abstract: A pulsed arbitration system has a partial-address coincidence detector with a partial-address collision flag as an output. An active global word line detector and disable pulse generator receives the partial-address collision flag as well as a decoded row address and an internal write pulse as an input, and generates a disable pulse for the interfering global word line of the colliding reading port.

Abstract: An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register and output from a selector circuit, such as a multiplexer, when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter, the external address, or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.