Patents by Inventor Stefan Dünkel
Stefan Dünkel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120420Abstract: Structures including a ferroelectric field-effect transistor and methods of forming a structure including a ferroelectric field-effect transistor. The structure comprises a semiconductor substrate, a semiconductor layer, a dielectric layer arranged between the semiconductor layer and the semiconductor substrate, and first and second wells in the semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. A ferroelectric field-effect transistor comprises a gate structure on the semiconductor layer over the first well and the second well. The gate structure includes a ferroelectric layer comprising a ferroelectric material.Type: ApplicationFiled: October 5, 2022Publication date: April 11, 2024Inventors: Stefan Dünkel, Dominik Martin Kleimaier, Zhixing Zhao, Halid Mulaosmanovic
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Publication number: 20240014320Abstract: Structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor. The structure comprises a gate stack having a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Inventors: Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Joachim Metzger, Robert Binder
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Publication number: 20230395605Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).Type: ApplicationFiled: August 21, 2023Publication date: December 7, 2023Inventors: Stefan Dünkel, Dominik M. Kleimaier
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Patent number: 11825663Abstract: A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.Type: GrantFiled: August 17, 2021Date of Patent: November 21, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Johannes Müller, Thomas Melde, Stefan Dünkel, Ralf Richter
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Patent number: 11817457Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).Type: GrantFiled: January 7, 2021Date of Patent: November 14, 2023Assignee: GlobalFoundries Dresden Module One Limited Liability Company & Co. KGInventors: Stefan Dünkel, Dominik M. Kleimaier
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Patent number: 11631772Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.Type: GrantFiled: January 13, 2021Date of Patent: April 18, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Thomas Melde, Stefan Dünkel, Ralf Richter
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Publication number: 20230067884Abstract: A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.Type: ApplicationFiled: August 17, 2021Publication date: March 2, 2023Inventors: JOHANNES MÜLLER, THOMAS MELDE, STEFAN DÜNKEL, RALF RICHTER
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Publication number: 20220223740Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.Type: ApplicationFiled: January 13, 2021Publication date: July 14, 2022Inventors: Thomas Melde, Stefan Dünkel, Ralf Richter
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Publication number: 20220216237Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).Type: ApplicationFiled: January 7, 2021Publication date: July 7, 2022Applicant: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KGInventors: Stefan Dünkel, Dominik M. Kleimaier
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Patent number: 10727251Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.Type: GrantFiled: December 3, 2018Date of Patent: July 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Stefan Dünkel, Johannes Müller, Lars Müller-Meskamp
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Publication number: 20200176456Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.Type: ApplicationFiled: December 3, 2018Publication date: June 4, 2020Inventors: Stefan DÜNKEL, Johannes MÜLLER, Lars MÜLLER-MESKAMP
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Patent number: 10388514Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.Type: GrantFiled: October 11, 2017Date of Patent: August 20, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Lars Mueller-Meskamp, Stefan Duenkel
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Patent number: 10319732Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.Type: GrantFiled: June 14, 2017Date of Patent: June 11, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu
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Publication number: 20190108998Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.Type: ApplicationFiled: October 11, 2017Publication date: April 11, 2019Inventors: Lars Mueller-Meskamp, Stefan Duenkel
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Patent number: 10176859Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.Type: GrantFiled: May 3, 2017Date of Patent: January 8, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Duenkel, Ralf Illgen, Ralf Richter, Soeren Jansen
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Patent number: 10163933Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.Type: GrantFiled: August 14, 2017Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Ralf Richter, Stefan Dünkel, Martin Trentzsch, Sven Beyer
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Publication number: 20180366484Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.Type: ApplicationFiled: June 14, 2017Publication date: December 20, 2018Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu
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Publication number: 20180322912Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.Type: ApplicationFiled: May 3, 2017Publication date: November 8, 2018Inventors: Stefan Duenkel, Ralf Illgen, Ralf Richter, Soeren Jansen
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Patent number: 10033383Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.Type: GrantFiled: March 20, 2017Date of Patent: July 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Ralf Richter, Stefan Duenkel, Sven Beyer