Patents by Inventor Stefan Duenkel

Stefan Duenkel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220223740
    Abstract: A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 14, 2022
    Inventors: Thomas Melde, Stefan Dünkel, Ralf Richter
  • Publication number: 20220216237
    Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).
    Type: Application
    Filed: January 7, 2021
    Publication date: July 7, 2022
    Applicant: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG
    Inventors: Stefan Dünkel, Dominik M. Kleimaier
  • Patent number: 10727251
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stefan Dünkel, Johannes Müller, Lars Müller-Meskamp
  • Publication number: 20200176456
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 4, 2020
    Inventors: Stefan DÜNKEL, Johannes MÜLLER, Lars MÜLLER-MESKAMP
  • Patent number: 10388514
    Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lars Mueller-Meskamp, Stefan Duenkel
  • Patent number: 10319732
    Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu
  • Publication number: 20190108998
    Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.
    Type: Application
    Filed: October 11, 2017
    Publication date: April 11, 2019
    Inventors: Lars Mueller-Meskamp, Stefan Duenkel
  • Patent number: 10176859
    Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Duenkel, Ralf Illgen, Ralf Richter, Soeren Jansen
  • Patent number: 10163933
    Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Stefan Dünkel, Martin Trentzsch, Sven Beyer
  • Publication number: 20180366484
    Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Inventors: Ralf Richter, Jochen Willi. Poth, Sven Beyer, Stefan Duenkel, Sandhya Chandrashekhar, Zhi-Yuan Wu
  • Publication number: 20180322912
    Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 8, 2018
    Inventors: Stefan Duenkel, Ralf Illgen, Ralf Richter, Soeren Jansen
  • Patent number: 10033383
    Abstract: In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 24, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Stefan Duenkel, Sven Beyer